[PATCH] D116917: [RISCV] Optimize some mul operation using SH*ADDUW instruction

[WangLian via Phabricator via llvm-commits]

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I saw this patch (https://reviews.llvm.org/D105796) optimize some mul operation with SH*ADD instruction. 
so, I think this maybe also apply to SH*ADDUW.

value = rs1 & 0xFFFFFFFF
(mul value, 3 * power_of_2) -> (SLLI (SH1ADDUW value, value), bits)
(mul value, 5 * power_of_2) -> (SLLI (SH2ADDUW value, value), bits)
(mul value, 9 * power_of_2) -> (SLLI (SH3ADDUW value, value), bits)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116917

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv64zba.ll


Index: llvm/test/CodeGen/RISCV/rv64zba.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zba.ll
+++ llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -525,6 +525,63 @@
   ret i64 %c
 }
 
+define i64 @mul96_2(i32 %a) {
+; RV64I-LABEL: mul96_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 3
+; RV64I-NEXT:    slli a1, a1, 37
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    mulhu a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul96_2:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh1add.uw a0, a0, a0
+; RV64ZBA-NEXT:    slli a0, a0, 5
+; RV64ZBA-NEXT:    ret
+  %b = zext i32 %a to i64
+  %c = mul i64 %b, 96
+  ret i64 %c
+}
+
+define i64 @mul160_2(i32 %a) {
+; RV64I-LABEL: mul160_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 5
+; RV64I-NEXT:    slli a1, a1, 37
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    mulhu a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul160_2:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh2add.uw a0, a0, a0
+; RV64ZBA-NEXT:    slli a0, a0, 5
+; RV64ZBA-NEXT:    ret
+  %b = zext i32 %a to i64
+  %c = mul i64 %b, 160
+  ret i64 %c
+}
+
+define i64 @mul288_2(i32 %a) {
+; RV64I-LABEL: mul288_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 9
+; RV64I-NEXT:    slli a1, a1, 37
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    mulhu a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul288_2:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh3add.uw a0, a0, a0
+; RV64ZBA-NEXT:    slli a0, a0, 5
+; RV64ZBA-NEXT:    ret
+  %b = zext i32 %a to i64
+  %c = mul i64 %b, 288
+  ret i64 %c
+}
+
 define i64 @sh1add_imm(i64 %0) {
 ; RV64I-LABEL: sh1add_imm:
 ; RV64I:       # %bb.0:
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1047,6 +1047,16 @@
           (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2)),
           (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(i64 (mul (and GPR:$r, 0xFFFFFFFF), C3LeftShift:$i)),
+          (SLLI (SH1ADDUW GPR:$r, GPR:$r),
+                (TrailingZerosXForm C3LeftShift:$i))>;
+def : Pat<(i64 (mul (and GPR:$r, 0xFFFFFFFF), C5LeftShift:$i)),
+          (SLLI (SH2ADDUW GPR:$r, GPR:$r),
+                (TrailingZerosXForm C5LeftShift:$i))>;
+def : Pat<(i64 (mul (and GPR:$r, 0xFFFFFFFF), C9LeftShift:$i)),
+          (SLLI (SH3ADDUW GPR:$r, GPR:$r),
+                (TrailingZerosXForm C9LeftShift:$i))>;
 } // Predicates = [HasStdExtZba, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {


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