[llvm] 2dd52f8 - [RISCV] Fold (srl (and X, 0xffff), C)->(srli (slli X, (XLen-16), (XLen-16) + C) even with Zbb/Zbp.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 9 18:44:12 PST 2022
Author: Craig Topper
Date: 2022-01-09T18:42:03-08:00
New Revision: 2dd52f840b9b9b66e06c32f706d6b31134435efe
URL: https://github.com/llvm/llvm-project/commit/2dd52f840b9b9b66e06c32f706d6b31134435efe
DIFF: https://github.com/llvm/llvm-project/commit/2dd52f840b9b9b66e06c32f706d6b31134435efe.diff
LOG: [RISCV] Fold (srl (and X, 0xffff), C)->(srli (slli X, (XLen-16), (XLen-16) + C) even with Zbb/Zbp.
We can use zext.h with Zbb, but srli/slli may offer more opportunities
for compression.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/div-by-constant.ll
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 3e43dfbef8847..dba6932394308 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -534,9 +534,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
return;
}
case ISD::SRL: {
- // We don't need this transform if zext.h is supported.
- if (Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp())
- break;
// Optimize (srl (and X, 0xffff), C) ->
// (srli (slli X, (XLen-16), (XLen-16) + C)
// Taking into account that the 0xffff may have had lower bits unset by
diff --git a/llvm/test/CodeGen/RISCV/div-by-constant.ll b/llvm/test/CodeGen/RISCV/div-by-constant.ll
index 85c3603167a81..50df79f85eaea 100644
--- a/llvm/test/CodeGen/RISCV/div-by-constant.ll
+++ b/llvm/test/CodeGen/RISCV/div-by-constant.ll
@@ -272,8 +272,8 @@ define i16 @udiv16_constant_add(i16 %a) nounwind {
; RV32IMZB-NEXT: mul a1, a1, a2
; RV32IMZB-NEXT: srli a1, a1, 16
; RV32IMZB-NEXT: sub a0, a0, a1
-; RV32IMZB-NEXT: zext.h a0, a0
-; RV32IMZB-NEXT: srli a0, a0, 1
+; RV32IMZB-NEXT: slli a0, a0, 16
+; RV32IMZB-NEXT: srli a0, a0, 17
; RV32IMZB-NEXT: add a0, a0, a1
; RV32IMZB-NEXT: srli a0, a0, 2
; RV32IMZB-NEXT: ret
@@ -299,8 +299,8 @@ define i16 @udiv16_constant_add(i16 %a) nounwind {
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
; RV64IMZB-NEXT: subw a0, a0, a1
-; RV64IMZB-NEXT: zext.h a0, a0
-; RV64IMZB-NEXT: srli a0, a0, 1
+; RV64IMZB-NEXT: slli a0, a0, 48
+; RV64IMZB-NEXT: srli a0, a0, 49
; RV64IMZB-NEXT: add a0, a0, a1
; RV64IMZB-NEXT: srli a0, a0, 2
; RV64IMZB-NEXT: ret
@@ -872,8 +872,8 @@ define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
; RV32IMZB-NEXT: mul a1, a1, a2
; RV32IMZB-NEXT: srli a1, a1, 16
; RV32IMZB-NEXT: add a0, a1, a0
-; RV32IMZB-NEXT: zext.h a1, a0
-; RV32IMZB-NEXT: srli a1, a1, 15
+; RV32IMZB-NEXT: slli a1, a0, 16
+; RV32IMZB-NEXT: srli a1, a1, 31
; RV32IMZB-NEXT: sext.h a0, a0
; RV32IMZB-NEXT: srai a0, a0, 3
; RV32IMZB-NEXT: add a0, a0, a1
@@ -902,8 +902,8 @@ define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
; RV64IMZB-NEXT: addw a0, a1, a0
-; RV64IMZB-NEXT: zext.h a1, a0
-; RV64IMZB-NEXT: srli a1, a1, 15
+; RV64IMZB-NEXT: slli a1, a0, 48
+; RV64IMZB-NEXT: srli a1, a1, 63
; RV64IMZB-NEXT: sext.h a0, a0
; RV64IMZB-NEXT: srai a0, a0, 3
; RV64IMZB-NEXT: add a0, a0, a1
@@ -938,8 +938,8 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV32IMZB-NEXT: mul a1, a1, a2
; RV32IMZB-NEXT: srli a1, a1, 16
; RV32IMZB-NEXT: sub a0, a1, a0
-; RV32IMZB-NEXT: zext.h a1, a0
-; RV32IMZB-NEXT: srli a1, a1, 15
+; RV32IMZB-NEXT: slli a1, a0, 16
+; RV32IMZB-NEXT: srli a1, a1, 31
; RV32IMZB-NEXT: sext.h a0, a0
; RV32IMZB-NEXT: srai a0, a0, 3
; RV32IMZB-NEXT: add a0, a0, a1
@@ -968,8 +968,8 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
; RV64IMZB-NEXT: subw a0, a1, a0
-; RV64IMZB-NEXT: zext.h a1, a0
-; RV64IMZB-NEXT: srli a1, a1, 15
+; RV64IMZB-NEXT: slli a1, a0, 48
+; RV64IMZB-NEXT: srli a1, a1, 63
; RV64IMZB-NEXT: sext.h a0, a0
; RV64IMZB-NEXT: srai a0, a0, 3
; RV64IMZB-NEXT: add a0, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
index 452de04563f0c..ed9252f6409fe 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
@@ -514,6 +514,8 @@ define i8 @srai_i8(i8 %a) nounwind {
ret i8 %1
}
+; We could use zext.h+srli, but slli+srli offers more opportunities for
+; comppressed instructions.
define i16 @srli_i16(i16 %a) nounwind {
; RV32I-LABEL: srli_i16:
; RV32I: # %bb.0:
@@ -523,14 +525,14 @@ define i16 @srli_i16(i16 %a) nounwind {
;
; RV32ZBB-LABEL: srli_i16:
; RV32ZBB: # %bb.0:
-; RV32ZBB-NEXT: zext.h a0, a0
-; RV32ZBB-NEXT: srli a0, a0, 6
+; RV32ZBB-NEXT: slli a0, a0, 16
+; RV32ZBB-NEXT: srli a0, a0, 22
; RV32ZBB-NEXT: ret
;
; RV32ZBP-LABEL: srli_i16:
; RV32ZBP: # %bb.0:
-; RV32ZBP-NEXT: zext.h a0, a0
-; RV32ZBP-NEXT: srli a0, a0, 6
+; RV32ZBP-NEXT: slli a0, a0, 16
+; RV32ZBP-NEXT: srli a0, a0, 22
; RV32ZBP-NEXT: ret
%1 = lshr i16 %a, 6
ret i16 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
index dc9c37b2ba6ce..23efb3bf9ebc7 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
@@ -585,6 +585,8 @@ define i8 @srai_i8(i8 %a) nounwind {
ret i8 %1
}
+; We could use zext.h+srli, but slli+srli offers more opportunities for
+; comppressed instructions.
define i16 @srli_i16(i16 %a) nounwind {
; RV64I-LABEL: srli_i16:
; RV64I: # %bb.0:
@@ -594,14 +596,14 @@ define i16 @srli_i16(i16 %a) nounwind {
;
; RV64ZBB-LABEL: srli_i16:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: zext.h a0, a0
-; RV64ZBB-NEXT: srli a0, a0, 6
+; RV64ZBB-NEXT: slli a0, a0, 48
+; RV64ZBB-NEXT: srli a0, a0, 54
; RV64ZBB-NEXT: ret
;
; RV64ZBP-LABEL: srli_i16:
; RV64ZBP: # %bb.0:
-; RV64ZBP-NEXT: zext.h a0, a0
-; RV64ZBP-NEXT: srli a0, a0, 6
+; RV64ZBP-NEXT: slli a0, a0, 48
+; RV64ZBP-NEXT: srli a0, a0, 54
; RV64ZBP-NEXT: ret
%1 = lshr i16 %a, 6
ret i16 %1
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