[PATCH] D116890: [RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng created this revision.
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Those two TTI hooks are used during vectorization for calculating
register pressure, the default implementation isn't consider for LMUL,
and that's also definitly wrong value for register number (all register class
are 8 registers).

So in this patch we tried to:

1. Calculate right register usage for vector type and scalar type.
2. Return right number of register for general purpose register and vector register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116890

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll

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