[PATCH] D116870: [SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, nikic.
Herald added subscribers: foad, ecnelises, dmgreen, hiraditya.
craig.topper requested review of this revision.
Herald added a project: LLVM.

These nodes should saturate to their saturating VT. We can use this
information to know the bits past the VT are all zeros or all sign bits.

I think we might only have test coverage for the unsigned case. I'll
verify and add tests.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116870

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/fcvt_combine.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
  llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
  llvm/test/CodeGen/Thumb2/mve-vcvt-float-to-fixed.ll

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