[llvm] f142c45 - [RISCV] Set getMinVectorRegisterBitWidth to 16 if enable fixed length vector code gen for RVV
Kito Cheng via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 7 19:16:27 PST 2022
Author: Kito Cheng
Date: 2022-01-08T11:16:21+08:00
New Revision: f142c45f1e494f8dbdcc1bcf14122d128ac8f3fe
URL: https://github.com/llvm/llvm-project/commit/f142c45f1e494f8dbdcc1bcf14122d128ac8f3fe
DIFF: https://github.com/llvm/llvm-project/commit/f142c45f1e494f8dbdcc1bcf14122d128ac8f3fe.diff
LOG: [RISCV] Set getMinVectorRegisterBitWidth to 16 if enable fixed length vector code gen for RVV
getMinVectorRegisterBitWidth means what vector types is supported in
this target, and actually RISC-V support all fixed length vector types with
vector length less than `getMinRVVVectorSizeInBits`, so set it to 16,
means 2 x i8, that is minimal fixed length vector size in theory.
That also fixed one issue, some testcase migth become non-vectorizable
when `-riscv-v-vector-bits-min` set to larger value, because the vector size is
smaller than `-riscv-v-vector-bits-min`.
For example, following code can vectorize by SLP with
`-riscv-v-vector-bits-min=128` or `-riscv-v-vector-bits-min=256`, but
can't vectorize `-riscv-v-vector-bits-min=512` or larger:
```
void foo(double *da) {
da[0] = 0;
da[1] = 1;
da[2] = 2;
da[3] = 3;
}
```
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D116534
Added:
llvm/test/Transforms/SLPVectorizer/RISCV/lit.local.cfg
llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll
Modified:
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 7353496f4684e..f9e33f4e328dc 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -81,7 +81,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
TTI::PeelingPreferences &PP);
unsigned getMinVectorRegisterBitWidth() const {
- return ST->hasVInstructions() ? ST->getMinRVVVectorSizeInBits() : 0;
+ return ST->useRVVForFixedLengthVectors() ? 16 : 0;
}
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/lit.local.cfg b/llvm/test/Transforms/SLPVectorizer/RISCV/lit.local.cfg
new file mode 100644
index 0000000000000..c63820126f8ca
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'RISCV' in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll
new file mode 100644
index 0000000000000..b40562f8f5768
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll
@@ -0,0 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+experimental-v \
+; RUN: -riscv-v-vector-bits-min=128 -S | FileCheck %s --check-prefixes=CHECK,CHECK-128
+; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+experimental-v \
+; RUN: -riscv-v-vector-bits-min=256 -S | FileCheck %s --check-prefixes=CHECK,CHECK-256
+; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+experimental-v \
+; RUN: -riscv-v-vector-bits-min=512 -S | FileCheck %s --check-prefixes=CHECK,CHECK-512
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64"
+
+define void @foo(i64* nocapture writeonly %da) {
+; CHECK-128-LABEL: @foo(
+; CHECK-128-NEXT: entry:
+; CHECK-128-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, i64* [[DA:%.*]], i64 1
+; CHECK-128-NEXT: [[TMP0:%.*]] = bitcast i64* [[DA]] to <2 x i64>*
+; CHECK-128-NEXT: store <2 x i64> <i64 0, i64 1>, <2 x i64>* [[TMP0]], align 8
+; CHECK-128-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 2
+; CHECK-128-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 3
+; CHECK-128-NEXT: [[TMP1:%.*]] = bitcast i64* [[ARRAYIDX2]] to <2 x i64>*
+; CHECK-128-NEXT: store <2 x i64> <i64 2, i64 3>, <2 x i64>* [[TMP1]], align 8
+; CHECK-128-NEXT: ret void
+;
+; CHECK-256-LABEL: @foo(
+; CHECK-256-NEXT: entry:
+; CHECK-256-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, i64* [[DA:%.*]], i64 1
+; CHECK-256-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 2
+; CHECK-256-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 3
+; CHECK-256-NEXT: [[TMP0:%.*]] = bitcast i64* [[DA]] to <4 x i64>*
+; CHECK-256-NEXT: store <4 x i64> <i64 0, i64 1, i64 2, i64 3>, <4 x i64>* [[TMP0]], align 8
+; CHECK-256-NEXT: ret void
+;
+; CHECK-512-LABEL: @foo(
+; CHECK-512-NEXT: entry:
+; CHECK-512-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, i64* [[DA:%.*]], i64 1
+; CHECK-512-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 2
+; CHECK-512-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* [[DA]], i64 3
+; CHECK-512-NEXT: [[TMP0:%.*]] = bitcast i64* [[DA]] to <4 x i64>*
+; CHECK-512-NEXT: store <4 x i64> <i64 0, i64 1, i64 2, i64 3>, <4 x i64>* [[TMP0]], align 8
+; CHECK-512-NEXT: ret void
+;
+entry:
+ store i64 0, i64* %da, align 8
+ %arrayidx1 = getelementptr inbounds i64, i64* %da, i64 1
+ store i64 1, i64* %arrayidx1, align 8
+ %arrayidx2 = getelementptr inbounds i64, i64* %da, i64 2
+ store i64 2, i64* %arrayidx2, align 8
+ %arrayidx3 = getelementptr inbounds i64, i64* %da, i64 3
+ store i64 3, i64* %arrayidx3, align 8
+ ret void
+}
+
+define void @foo8(i8* nocapture writeonly %da) {
+; CHECK-LABEL: @foo8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[DA:%.*]], i8 1
+; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[DA]] to <2 x i8>*
+; CHECK-NEXT: store <2 x i8> <i8 0, i8 1>, <2 x i8>* [[TMP0]], align 8
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[DA]], i8 2
+; CHECK-NEXT: ret void
+;
+entry:
+ store i8 0, i8* %da, align 8
+ %arrayidx1 = getelementptr inbounds i8, i8* %da, i8 1
+ store i8 1, i8* %arrayidx1, align 8
+ %arrayidx2 = getelementptr inbounds i8, i8* %da, i8 2
+ ret void
+}
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