[PATCH] D116534: [RISCV] Set getMinVectorRegisterBitWidth to 16 if enable fixed length vector code gen for RVV

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 7 17:57:15 PST 2022

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craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116534/new/

https://reviews.llvm.org/D116534

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