[PATCH] D116534: [RISCV] Set getMinVectorRegisterBitWidth to 16 if enable fixed length vector code gen for RVV

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I agree it shouldn't be based on -riscv-v-vector-bits-min. But 16 feels maybe too low. What do other targets use?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D116534/new/

https://reviews.llvm.org/D116534