[PATCH] D116270: [AMDGPU] Enable divergence-driven XNOR selection

[Alexander via Phabricator via llvm-commits]

alex-t added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:924
+
+MachineBasicBlock::iterator SIFixSGPRCopies::processVNOT(MachineInstr &MI) {
+  MachineBasicBlock::iterator I(MI);
----------------
foad wrote:
> I have not read this code but it looks very complicated. I think this would be much better done as a DAG combine analogous to the existing SITargetLowering::reassociateScalarOps -- which is about 1/5th of the size of this function!
This is not about the DAG at all. And this is not about the DAG combine.
SITargetLowering::reassociateScalarOps exists to fix the instruction selection that is done in a wrong way. The instruction selection in LC was initially done incorrectly.
Namely, everything is selected to the SALU and then manually lowered to VALU if there is at least one VGPR to SGPR copy. The whole work I am trying to do here is to change this so that we explicitly select the correct form of the instruction. This function is 5 times larger just because it includes all things done in reassociateScalarOps and the corresponding moveToVALU logic.



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  https://reviews.llvm.org/D116270/new/

https://reviews.llvm.org/D116270