[PATCH] D116375: [X86] Use bit test instructions to optimize some logic atomic operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:30894
+          continue;
+        if (C2 || UI->getOpcode() != ISD::AND)
+          report_fatal_error("Atomic result must be used by one AND");
----------------
Verify that operand 1 is a constant too.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:30895
+        if (C2 || UI->getOpcode() != ISD::AND)
+          report_fatal_error("Atomic result must be used by one AND");
+        C2 = cast<ConstantSDNode>(UI->getOperand(1));
----------------
My big concern is that we rely on the checks done in IR holding until SelectionDAG. If that fails and a user hits this fatal error, how would they know how to fix their code?

Did you give any thought about converting the patterns into a target specific intrinsic in IR? That would probably need to be a new hook in the AtomicExpandPass or a separate X86 pass.

@rksimon or @spatel what are your thoughts?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116375/new/

https://reviews.llvm.org/D116375