[llvm] 1f71e46 - [Hexagon] Apply tiny core packet size slots limit

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Fri Jan 7 10:33:25 PST 2022


Author: Brian Cain
Date: 2022-01-07T10:33:12-08:00
New Revision: 1f71e46f2a4fd34197607a4f59c3c93576b005a3

URL: https://github.com/llvm/llvm-project/commit/1f71e46f2a4fd34197607a4f59c3c93576b005a3
DIFF: https://github.com/llvm/llvm-project/commit/1f71e46f2a4fd34197607a4f59c3c93576b005a3.diff

LOG: [Hexagon] Apply tiny core packet size slots limit

Added: 
    llvm/test/MC/Hexagon/bug18767.s

Modified: 
    llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
    llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
index 2ce791a450a85..84f62da269b6b 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
@@ -378,18 +378,8 @@ bool HexagonMCChecker::checkCOFMax1() {
 }
 
 bool HexagonMCChecker::checkSlots() {
-  unsigned slotsUsed = 0;
-  for (auto HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
-    MCInst const &MCI = *HMI.getInst();
-    if (HexagonMCInstrInfo::isImmext(MCI))
-      continue;
-    if (HexagonMCInstrInfo::isDuplex(MCII, MCI))
-      slotsUsed += 2;
-    else
-      ++slotsUsed;
-  }
-
-  if (slotsUsed > HEXAGON_PACKET_SIZE) {
+  if (HexagonMCInstrInfo::slotsConsumed(MCII, STI, MCB) >
+      HexagonMCInstrInfo::packetSizeSlots(STI)) {
     reportError("invalid instruction packet: out of slots");
     return false;
   }

diff  --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
index 7e0dea6be7d20..66e84e115eba2 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
@@ -326,8 +326,7 @@ unsigned packetSizeSlots(MCSubtargetInfo const &STI);
 unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
                        MCInst const &MCI);
 
-
-// Pad the bundle with nops to satisfy endloop requirements
+// Pad the bundle with nops to satisfy endloop requirements.
 void padEndloop(MCInst &MCI, MCContext &Context);
 class PredicateInfo {
 public:

diff  --git a/llvm/test/MC/Hexagon/bug18767.s b/llvm/test/MC/Hexagon/bug18767.s
new file mode 100644
index 0000000000000..35604f379cacf
--- /dev/null
+++ b/llvm/test/MC/Hexagon/bug18767.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s < %t
+
+.L_:
+{
+  loop0(.L_,r2);
+  r7=r1;
+  r5=mpyi(r1,#64);
+  r6=#0;
+  nop;
+}
+# CHECK: rror: invalid instruction packet: out of slots


        


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