[llvm] a58a062 - [Hexagon] Show slot resources for errors

[Krzysztof Parzyszek via llvm-commits]

Author: Brian Cain
Date: 2022-01-07T08:27:33-08:00
New Revision: a58a062fbae06c1d268740f7c9c2137526344c4f

URL: https://github.com/llvm/llvm-project/commit/a58a062fbae06c1d268740f7c9c2137526344c4f
DIFF: https://github.com/llvm/llvm-project/commit/a58a062fbae06c1d268740f7c9c2137526344c4f.diff

LOG: [Hexagon] Show slot resources for errors

For a scalar packet resource error, emit details about the slots
available for each instruction in the packet.

Added: 
    llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store.s

Modified: 
    llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
    llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
index 019b8a62b99c9..e3d3c81f1361e 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
@@ -304,7 +304,7 @@ void HexagonShuffler::restrictBranchOrder(HexagonPacketSummary const &Summary) {
     Packet = PacketSave;
   }
 
-  reportError("invalid instruction packet: out of slots");
+  reportResourceError(Summary, "out of slots");
 }
 
 void HexagonShuffler::permitNonSlot() {
@@ -319,7 +319,7 @@ bool HexagonShuffler::ValidResourceUsage(HexagonPacketSummary const &Summary) {
   Optional<HexagonPacket> ShuffledPacket = tryAuction(Summary);
 
   if (!ShuffledPacket) {
-    reportError("invalid instruction packet: slot error");
+    reportResourceError(Summary, "slot error");
     return false;
   }
 
@@ -439,6 +439,15 @@ bool HexagonShuffler::restrictStoreLoadOrder(
   return true;
 }
 
+static std::string SlotMaskToText(unsigned SlotMask) {
+    SmallVector<std::string, HEXAGON_PRESHUFFLE_PACKET_SIZE> Slots;
+    for (unsigned SlotNum = 0; SlotNum < HEXAGON_PACKET_SIZE; SlotNum++)
+        if ((SlotMask & (1 << SlotNum)) != 0)
+            Slots.push_back(utostr(SlotNum));
+
+    return llvm::join(Slots, StringRef(", "));
+}
+
 HexagonShuffler::HexagonPacketSummary HexagonShuffler::GetPacketSummary() {
   HexagonPacketSummary Summary = HexagonPacketSummary();
 
@@ -455,8 +464,13 @@ HexagonShuffler::HexagonPacketSummary HexagonShuffler::GetPacketSummary() {
       ++Summary.pSlot3Cnt;
       Summary.PrefSlot3Inst = ISJ;
     }
-    Summary.ReservedSlotMask |=
+    const unsigned ReservedSlots =
         HexagonMCInstrInfo::getOtherReservedSlots(MCII, STI, ID);
+    Summary.ReservedSlotMask |= ReservedSlots;
+    if (ReservedSlots != 0)
+      AppliedRestrictions.push_back(std::make_pair(ID.getLoc(),
+                  (Twine("Instruction has reserved slots: ") +
+                   SlotMaskToText(ReservedSlots)).str()));
 
     switch (HexagonMCInstrInfo::getType(MCII, ID)) {
     case HexagonII::TypeS_2op:
@@ -639,7 +653,7 @@ bool HexagonShuffler::shuffle() {
   if (size() > HEXAGON_PACKET_SIZE) {
     // Ignore a packet with with more than what a packet can hold
     // or with compound or duplex insns for now.
-    reportError(Twine("invalid instruction packet"));
+    reportError("invalid instruction packet");
     return false;
   }
 
@@ -688,6 +702,32 @@ bool HexagonShuffler::shuffle() {
   return Ok;
 }
 
+void HexagonShuffler::reportResourceError(HexagonPacketSummary const &Summary, StringRef Err) {
+  if (ReportErrors)
+    reportResourceUsage(Summary);
+  reportError(Twine("invalid instruction packet: ") + Err);
+}
+
+
+void HexagonShuffler::reportResourceUsage(HexagonPacketSummary const &Summary) {
+  auto SM = Context.getSourceManager();
+  if (SM) {
+    for (HexagonInstr const &I : insts()) {
+      const unsigned Units = I.Core.getUnits();
+
+      if (HexagonMCInstrInfo::requiresSlot(STI, *I.ID)) {
+        const std::string UnitsText = Units ? SlotMaskToText(Units) : "<None>";
+        SM->PrintMessage(I.ID->getLoc(), SourceMgr::DK_Note,
+                Twine("Instruction can utilize slots: ") +
+                UnitsText);
+      }
+      else if (!HexagonMCInstrInfo::isImmext(*I.ID))
+        SM->PrintMessage(I.ID->getLoc(), SourceMgr::DK_Note,
+                       "Instruction does not require a slot");
+    }
+  }
+}
+
 void HexagonShuffler::reportError(Twine const &Msg) {
   CheckFailure = true;
   if (ReportErrors) {

diff  --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
index d28d8e9dbaa46..70992e4c7e810 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
@@ -72,16 +72,6 @@ class HexagonCVIResource : public HexagonResource {
   using UnitsAndLanes = std::pair<unsigned, unsigned>;
 
 private:
-  // Available HVX slots.
-  enum {
-    CVI_NONE = 0,
-    CVI_XLANE = 1 << 0,
-    CVI_SHIFT = 1 << 1,
-    CVI_MPY0 = 1 << 2,
-    CVI_MPY1 = 1 << 3,
-    CVI_ZW = 1 << 4
-  };
-
   // Count of adjacent slots that the insn requires to be executed.
   unsigned Lanes;
   // Flag whether the insn is a load or a store.
@@ -244,6 +234,8 @@ class HexagonShuffler {
 
   // Return the error code for the last check or shuffling of the bundle.
   void reportError(Twine const &Msg);
+  void reportResourceError(HexagonPacketSummary const &Summary, StringRef Err);
+  void reportResourceUsage(HexagonPacketSummary const &Summary);
 };
 
 } // end namespace llvm

diff  --git a/llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store.s b/llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store.s
new file mode 100644
index 0000000000000..34a607c37be84
--- /dev/null
+++ b/llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store.s
@@ -0,0 +1,15 @@
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s
+
+{ r0=sub(#1,r0)
+  r1=sub(#1, r0)
+  memw(r0)=r0
+  if (p3) dealloc_return }
+
+
+# CHECK: note: Instruction can utilize slots: 0, 1, 2, 3
+# CHECK: note: Instruction can utilize slots: 0, 1, 2, 3
+# CHECK: note: Instruction can utilize slots: <None>
+# CHECK: note: Instruction can utilize slots: 0
+# CHECK: note: Instruction was restricted from being in slot 1
+# CHECK: note: Instruction does not allow a store in slot 1
+# CHECK: error: invalid instruction packet: slot error