[PATCH] D114357: [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

[David Sherwood via Phabricator via llvm-commits]

david-arm updated this revision to Diff 398142.
david-arm retitled this revision from "[CodeGen] Change getAnyExtOrTrunc to use SIGN_EXTEND for some constants" to "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants".
david-arm edited the summary of this revision.
david-arm added a comment.
Herald added subscribers: luke957, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.

- Rewrote the patch to make use of `isSExtCheaperThanZExt` instead so that this becomes a AArch64-specific change.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114357/new/

https://reviews.llvm.org/D114357

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/CodeGenPrepare.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
  llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
  llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
  llvm/test/CodeGen/AArch64/dag-numsignbits.ll
  llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
  llvm/test/CodeGen/AArch64/funnel-shift.ll
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/redundant-copy-elim-empty-mbb.ll
  llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
  llvm/test/CodeGen/AArch64/sve-vector-splat.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll

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