[PATCH] D40554: [PowerPC] Fix bugs in sign-/zero-extension elimination

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:5092
 
 // This function returns true if the machine instruction
 // always outputs a value by sign-extending a 32 bit value,
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Question: should we update this to say if the `register` and not `machine instruction` since it is changed to `Reg` for the parameter? 
Or should it stay as machine instruction since you're checking for the different `MachineInstr` opcodes in this function?
The same question I have applies to `definedByZeroExtendingOp()`.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:5129
 
+  // RLDICL generates sign-extended output if it cleares at least
+  // 33 bits from the left (MSB).
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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:5314
+    auto SrcExt = isSignOrZeroExtended(SrcReg, BinOpDepth, MRI);
+    return std::pair<bool, bool>(SrcExt.first | IsSExt, SrcExt.second | IsZExt);
   }
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If the change to logical or still applies, we should probably update these accordingly.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D40554/new/

https://reviews.llvm.org/D40554