[PATCH] D114800: [PowerPC] Replace MFVSRLD with MFVSRD when the vector is symmetrical
Amy Kwan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 7 07:03:59 PST 2022
amyk added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:408
+
+ if (DefVecReg->getDesc().isCommutable()) {
+ MachineOperand &OpInput1 = DefVecReg->getOperand(1);
----------------
Maybe we can try an early exit if this works:
```
if (!DefVecReg->getDesc().isCommutable())
return false;
```
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D114800/new/
https://reviews.llvm.org/D114800
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