[llvm] 7a66c98 - [AMDGPU] Regenerate G_[SU]BFX checks using some common prefixes
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 7 04:07:13 PST 2022
Author: Jay Foad
Date: 2022-01-07T12:04:56Z
New Revision: 7a66c980f58be288c02a119055d8527508508164
URL: https://github.com/llvm/llvm-project/commit/7a66c980f58be288c02a119055d8527508508164
DIFF: https://github.com/llvm/llvm-project/commit/7a66c980f58be288c02a119055d8527508508164.diff
LOG: [AMDGPU] Regenerate G_[SU]BFX checks using some common prefixes
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
index afb2ebd5eb0db..1a4c7001b0438 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefixes=GCN,GFX89 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefixes=GCN,GFX89 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefixes=GCN,GFX10 %s
; Test vector signed bitfield extract.
define signext i8 @v_ashr_i8_i32(i32 %value) {
-; GCN-LABEL: v_ashr_i8_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_bfe_i32 v0, v0, 4, 8
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_ashr_i8_i32:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_bfe_i32 v0, v0, 4, 8
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ashr_i8_i32:
; GFX10: ; %bb.0:
@@ -23,11 +23,11 @@ define signext i8 @v_ashr_i8_i32(i32 %value) {
}
define signext i16 @v_ashr_i16_i32(i32 %value) {
-; GCN-LABEL: v_ashr_i16_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_bfe_i32 v0, v0, 9, 16
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_ashr_i16_i32:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_bfe_i32 v0, v0, 9, 16
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ashr_i16_i32:
; GFX10: ; %bb.0:
@@ -41,11 +41,11 @@ define signext i16 @v_ashr_i16_i32(i32 %value) {
}
define signext i8 @v_lshr_i8_i32(i32 %value) {
-; GCN-LABEL: v_lshr_i8_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_bfe_i32 v0, v0, 4, 8
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_lshr_i8_i32:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_bfe_i32 v0, v0, 4, 8
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i8_i32:
; GFX10: ; %bb.0:
@@ -59,11 +59,11 @@ define signext i8 @v_lshr_i8_i32(i32 %value) {
}
define signext i16 @v_lshr_i16_i32(i32 %value) {
-; GCN-LABEL: v_lshr_i16_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_bfe_i32 v0, v0, 9, 16
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_lshr_i16_i32:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_bfe_i32 v0, v0, 9, 16
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i16_i32:
; GFX10: ; %bb.0:
@@ -78,13 +78,13 @@ define signext i16 @v_lshr_i16_i32(i32 %value) {
; Test vector bitfield extract for 64-bits.
define i64 @v_ashr_i64(i64 %value) {
-; GCN-LABEL: v_ashr_i64:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]
-; GCN-NEXT: v_bfe_i32 v0, v0, 0, 4
-; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_ashr_i64:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]
+; GFX89-NEXT: v_bfe_i32 v0, v0, 0, 4
+; GFX89-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ashr_i64:
; GFX10: ; %bb.0:
@@ -101,13 +101,13 @@ define i64 @v_ashr_i64(i64 %value) {
}
define i64 @v_lshr_i64(i64 %value) {
-; GCN-LABEL: v_lshr_i64:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]
-; GCN-NEXT: v_bfe_i32 v0, v0, 0, 4
-; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_lshr_i64:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]
+; GFX89-NEXT: v_bfe_i32 v0, v0, 0, 4
+; GFX89-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i64:
; GFX10: ; %bb.0:
@@ -129,11 +129,6 @@ define amdgpu_ps signext i8 @s_ashr_i8_i32(i32 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_i32 s0, s0, 0x80004
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_ashr_i8_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_i32 s0, s0, 0x80004
-; GFX10-NEXT: ; return to shader part epilog
%1 = ashr i32 %value, 4
%2 = trunc i32 %1 to i8
ret i8 %2
@@ -144,11 +139,6 @@ define amdgpu_ps signext i16 @s_ashr_i16_i32(i32 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_i32 s0, s0, 0x100009
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_ashr_i16_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_i32 s0, s0, 0x100009
-; GFX10-NEXT: ; return to shader part epilog
%1 = ashr i32 %value, 9
%2 = trunc i32 %1 to i16
ret i16 %2
@@ -159,11 +149,6 @@ define amdgpu_ps signext i8 @s_lshr_i8_i32(i32 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_i32 s0, s0, 0x80004
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_lshr_i8_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_i32 s0, s0, 0x80004
-; GFX10-NEXT: ; return to shader part epilog
%1 = lshr i32 %value, 4
%2 = trunc i32 %1 to i8
ret i8 %2
@@ -174,11 +159,6 @@ define amdgpu_ps signext i16 @s_lshr_i16_i32(i32 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_i32 s0, s0, 0x100009
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_lshr_i16_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_i32 s0, s0, 0x100009
-; GFX10-NEXT: ; return to shader part epilog
%1 = lshr i32 %value, 9
%2 = trunc i32 %1 to i16
ret i16 %2
@@ -190,11 +170,6 @@ define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x40001
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_ashr_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x40001
-; GFX10-NEXT: ; return to shader part epilog
%1 = ashr i64 %value, 1
%2 = shl i64 %1, 60
%3 = ashr i64 %2, 60
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
index d4657dfc2b506..bb312b038ddfe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll
@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefixes=GCN,GFX89 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefixes=GCN,GFX89 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefixes=GCN,GFX10 %s
; Test vector bitfield extract.
define i32 @v_srl_mask_i32(i32 %value) {
-; GCN-LABEL: v_srl_mask_i32:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_bfe_u32 v0, v0, 8, 5
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_srl_mask_i32:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_bfe_u32 v0, v0, 8, 5
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_srl_mask_i32:
; GFX10: ; %bb.0:
@@ -28,11 +28,6 @@ define amdgpu_ps i32 @s_srl_mask_i32(i32 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_u32 s0, s0, 0x50008
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_srl_mask_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x50008
-; GFX10-NEXT: ; return to shader part epilog
%1 = lshr i32 %value, 8
%2 = and i32 %1, 31
ret i32 %2
@@ -44,11 +39,6 @@ define amdgpu_ps i32 @s_srl_big_mask_i32(i32 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, 30
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_srl_big_mask_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshr_b32 s0, s0, 30
-; GFX10-NEXT: ; return to shader part epilog
%1 = lshr i32 %value, 30
%2 = and i32 %1, 31
ret i32 %2
@@ -56,13 +46,13 @@ define amdgpu_ps i32 @s_srl_big_mask_i32(i32 inreg %value) {
; Test vector bitfield extract for 64-bits.
define i64 @v_srl_mask_i64(i64 %value) {
-; GCN-LABEL: v_srl_mask_i64:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: v_lshrrev_b64 v[0:1], 25, v[0:1]
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: v_bfe_u32 v0, v0, 0, 10
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: v_srl_mask_i64:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: v_lshrrev_b64 v[0:1], 25, v[0:1]
+; GFX89-NEXT: v_mov_b32_e32 v1, 0
+; GFX89-NEXT: v_bfe_u32 v0, v0, 0, 10
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_srl_mask_i64:
; GFX10: ; %bb.0:
@@ -83,11 +73,6 @@ define amdgpu_ps i64 @s_srl_mask_i64(i64 inreg %value) {
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_u64 s[0:1], s[0:1], 0xa0019
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_srl_mask_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u64 s[0:1], s[0:1], 0xa0019
-; GFX10-NEXT: ; return to shader part epilog
%1 = lshr i64 %value, 25
%2 = and i64 %1, 1023
ret i64 %2
@@ -100,12 +85,6 @@ define amdgpu_ps i64 @s_srl_big_mask_i64(i64 inreg %value) {
; GCN-NEXT: s_lshr_b32 s0, s1, 28
; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: ; return to shader part epilog
-;
-; GFX10-LABEL: s_srl_big_mask_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshr_b32 s0, s1, 28
-; GFX10-NEXT: s_mov_b32 s1, 0
-; GFX10-NEXT: ; return to shader part epilog
%1 = lshr i64 %value, 60
%2 = and i64 %1, 63
ret i64 %2
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