[PATCH] D116791: [RISCV] Supplement PACKH instruction pattern

[WangLian via Phabricator via llvm-commits]

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lower = rs1 & 255
upper = (rs2 & 255) << 8
value = lower | upper


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116791

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

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