[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

[Shao-Ce SUN via Phabricator via llvm-commits]

achieveartificialintelligence added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCV.td:155-187
+def FeatureStdExtZvl64b : SubtargetFeature<"experimental-zvl64b", "ZvlLen", "ExtZvl::Zvl64b",
+                       "'Zvl' (Minimum Vector Length) 64",
+                       [FeatureStdExtZvl32b]>;
+def FeatureStdExtZvl128b : SubtargetFeature<"experimental-zvl128b", "ZvlLen", "ExtZvl::Zvl128b",
+                       "'Zvl' (Minimum Vector Length) 128",
+                       [FeatureStdExtZvl64b]>;
+def FeatureStdExtZvl256b : SubtargetFeature<"experimental-zvl256b", "ZvlLen", "ExtZvl::Zvl256b",
----------------
I think we can write in this way:
```
foreach i = { 5-15 } in {
  defvar I = !shl(2, i);
  def FeatureStdExtZvl#I#b
      : SubtargetFeature<"experimental-zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b",
                        "'Zvl' (Minimum Vector Length) "#I,
                        [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694