[PATCH] D116771: [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)

[Craig Topper via Phabricator via llvm-commits]

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Similar for ceil, trunc, round, and roundeven. This allows us to use
static rounding modes to avoid a libcall.

This optimization is done for AArch64 as isel patterns.
RISCV doesn't have instructions for ceil/floor/trunc/round/roundeven
so the operations don't stick around until isel to enable a pattern
match. Thus I've implemented a DAG combine.

We only handle XLen types except i32 on RV64. i32 will be type
legalized to a RISCVISD node. All other types will be type legalized
to XLen and maintain the FP_TO_SINT/UINT ISD opcode.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116771

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-round-conv.ll
  llvm/test/CodeGen/RISCV/float-round-conv.ll
  llvm/test/CodeGen/RISCV/half-round-conv.ll

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