[PATCH] D116727: [RISCV] Supplement SH*ADDUW instructions pattern

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:1039
           (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i64 (add (mul (and GPR:$rs1, 0xFFFFFFFF), (i64 2)), non_imm12:$rs2)),
+          (SH1ADDUW GPR:$rs1, GPR:$rs2)>;
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jacquesguan wrote:
> Does the InstCombine canonicalize `mul X, 2` to `shl X, 1`? 
InstCombine and DAGCombine both canonicalize mul by power 2 to shifts.


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Comment at: llvm/test/CodeGen/RISCV/rv64zba.ll:210
 
+define i64 @sh1adduw_3(i64 %0, i64 %1) {
+; RV64I-LABEL: sh1adduw_3:
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These tests cases pass without your change


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D116727/new/

https://reviews.llvm.org/D116727