[PATCH] D116584: [RISCV] Block vmsgeu.vi with 0 immediate in Isel

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:841
         llvm_unreachable("Unexpected LMUL!");
       case RISCVII::VLMUL::LMUL_F8:
         VMSLTOpcode =
----------------
This code was recently changed to use a macro for each case since they are only vary by instruction suffix. Please rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116584/new/

https://reviews.llvm.org/D116584