[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

The DataLayout documentation says:

> This specifies a set of native integer widths for the target CPU in bits. For example, it might contain n32 for 32-bit PowerPC, n32:64 for PowerPC 64, or n8:16:32:64 for X86-64. Elements of this set are considered to support most general arithmetic operations efficiently.

It's unclear what exactly that means for RISC-V.

Having said that, for the IVUsers example pointed out, that's just bad code in LLVM, it should permit things that are smaller than native integers, I would imagine. Otherwise, say, i16, won't be used on most targets (other than X86 and a few experimental, embedded or graphics-y targets) as they'll only have n32:64, but the comment there is clearly to just stop it creating overly-//large// integer types.


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https://reviews.llvm.org/D116735