[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string
Alex Bradbury via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 6 07:55:09 PST 2022
asb added a comment.
Thanks - I don't think much thought has gone into whether n32:n64 would be reasonable for RV64, so I really appreciate you digging in to it.
I've only run this against the GCC torture suite, and on average this seems to be about neutral (or mildly positive). There are a few cases where code is worse though - it's possible this is simply unmasking an issue with poor codegen for 32-bit types (that would otherwise be promoted earlier), though I haven't investigated. e.g.
--- a/output_rv64imafdc_lp64_O1/930921-1.s
+++ b/output_rv64imafdc_lp64_O1/930921-1.s
@@ -24,18 +24,29 @@ main: # @main
# %bb.0: # %entry
addi sp, sp, -16
sd ra, 8(sp) # 8-byte Folded Spill
+ li a0, 0
li a1, 0
- li a0, 1
- lui a2, 2
- addiw a2, a2, 1806
+ lui a2, 699051
+ addiw a2, a2, -1365
+ slli a6, a2, 32
+ lui a3, 171
+ addiw a3, a3, -1365
+ slli a3, a3, 12
+ addi a3, a3, -1365
+ lui a4, 2
+ addiw a4, a4, 1808
.LBB1_1: # %for.body
# =>This Inner Loop Header: Depth=1
- beqz a0, .LBB1_4
+ srli a5, a0, 33
+ slli a2, a1, 32
+ mulhu a2, a2, a6
+ srli a2, a2, 33
+ bne a2, a5, .LBB1_4
# %bb.2: # %for.cond
# in Loop: Header=BB1_1 Depth=1
- sext.w a3, a1
addiw a1, a1, 1
- bgeu a2, a3, .LBB1_1
+ add a0, a0, a3
+ bne a1, a4, .LBB1_1
# %bb.3: # %for.end
li a0, 0
call exit
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D116735/new/
https://reviews.llvm.org/D116735
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