[PATCH] D116720: [RISCV] Use shift for zext.h when Zbb and Zbp are not enabled

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1045-1051
+// AND with mask exceeding simm12.
+let Predicates = [NotHasStdExtZbbOrZbp, IsRV32] in
+def : Pat<(i32 (and_const_oneuse GPR:$rs, 0xFFFF)),
+          (SRLI (SLLI $rs, 16), 16)>;
+let Predicates = [NotHasStdExtZbbOrZbp, IsRV64] in
+def : Pat<(i64 (and_const_oneuse GPR:$rs, 0xFFFF)),
+          (SRLI (SLLI $rs, 48), 48)>;
----------------
You could generalise this to the input being a zero-extended all ones value and using a shift of XLen - number of ones, i.e. using isMask_64, countTrailingOnes and ImmSubFromXLen. That'd also result in a single pattern that works for both RV32 and RV64; RISCVInstrInfoB.td only has separate patterns because the RV32 and RV64 ZEXTH instructions are different.


Repository:
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  https://reviews.llvm.org/D116720/new/

https://reviews.llvm.org/D116720