[PATCH] D116424: [ShrinkWrap] check for PPC's non-callee-saved LR

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers added a comment.

In D116424#3223345 <https://reviews.llvm.org/D116424#3223345>, @efriedma wrote:

> Do we need coverage for lr use and/or def, in addition to clobber?

Can you help me come up with test cases? :-3

I would have guessed for a use+def:

  void x (void) {
      register int y asm("lr");
      asm (""::"r"(y));
  }

but that actually asserts during post-RA pseudo expansion: `Impossible reg-to-reg copy` (probably we're missing support for `mfspr`?).

I also would have guess there's perhaps intrinsics for accessing the `lr` on PPC; instead it seems that `mfspr` is used to read the PPC Special Purpose Registers (SPRs) into the General Purpose Registers (GPRs) IIUC.



================
Comment at: llvm/lib/CodeGen/ShrinkWrap.cpp:296
+      // want to shrinkwrap across such an MachineInstr.
+      if (!UseOrDefCSR && MO.isEarlyClobber()) {
+        const MachineFunction *MF = MI.getParent()->getParent();
----------------
FWIW: this special case is also implicit-def. The full MachineOperand is `implicit-def early-clobber $lr`.


================
Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.h:190
+  bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override {
+    return Reg == PPC::LR || Reg == PPC::LR8;
+  }
----------------
I should probably assert that PPC::LR and PPC::LR8 are not callee saved, since that's the whole point of this interface.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116424/new/

https://reviews.llvm.org/D116424