[PATCH] D116424: [PowerPC] add LR to CalleeSavedRegs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

In D116424#3223071 <https://reviews.llvm.org/D116424#3223071>, @nickdesaulniers wrote:

> In D116424#3222971 <https://reviews.llvm.org/D116424#3222971>, @efriedma wrote:
>
>> From the test changes, it looks like the current patch completely disables shrink-wrapping in all cases?  Or am I missing something?
>
> Doesn't `@loopInfoRestoreOutsideLoop` in llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll show that that's NOT the case? The `mflr`/`mtlr` pair are sunk+raised respectively since the entry block is conditional and doesn't use the stack.
>
> `@foo` in llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll also has an early return rather than an unconditional prolog. `bgelr` (branch to lr if greater than or equal to). Compared to the codegen with shrink wrap disabled, the `mflr`/`mtlr` pair is unconditional.
>
> Though I'm less convinced about `@@shrinkwrap` in llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll and `@test` in llvm/test/CodeGen/PowerPC/pr43527.ll.

Maybe verify that llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll shrink-wraps in both 32-bit and 64-bit modes?

In any case, the patch is clearly having some effect beside the one you're trying for.


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https://reviews.llvm.org/D116424