[PATCH] D116645: [RISCV][llvm] Update CSRs

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSystemOperands.td:176
-def : SysReg<"sedeleg", 0x102>;
-def : SysReg<"sideleg", 0x103>;
 def : SysReg<"sie", 0x104>;
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You've got rid of the S-mode N extension CSRs but not the U-mode ones. I don't know if we should be removing these or not; I do know of a soft-core that actually implements it.


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Comment at: llvm/lib/Target/RISCV/RISCVSystemOperands.td:180
+//===-------------------------------------------------------------------------//
+// Supervisor Trap Setup
+//===-------------------------------------------------------------------------//
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  https://reviews.llvm.org/D116645/new/

https://reviews.llvm.org/D116645