[llvm] 9566cf1 - [CSKY] Add codegen of select/br/cmp instruction and some frame lowering infra
Zi Xuan Wu via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 4 23:59:54 PST 2022
Author: Zi Xuan Wu
Date: 2022-01-05T15:59:03+08:00
New Revision: 9566cf16ad39b6060f14648e0f29182079650430
URL: https://github.com/llvm/llvm-project/commit/9566cf16ad39b6060f14648e0f29182079650430
DIFF: https://github.com/llvm/llvm-project/commit/9566cf16ad39b6060f14648e0f29182079650430.diff
LOG: [CSKY] Add codegen of select/br/cmp instruction and some frame lowering infra
Add basic integer codegen of select/br/cmp instruction. It also includes frame lowering code
such as prologue/epilogue.
Added:
llvm/test/CodeGen/CSKY/br.ll
llvm/test/CodeGen/CSKY/cmp-i.ll
llvm/test/CodeGen/CSKY/select.ll
Modified:
llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
llvm/lib/Target/CSKY/CSKYFrameLowering.h
llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
llvm/lib/Target/CSKY/CSKYISelLowering.cpp
llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
llvm/lib/Target/CSKY/CSKYInstrInfo.h
llvm/lib/Target/CSKY/CSKYInstrInfo.td
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp b/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
index 3a8ee5713584b..3bf001c2cee71 100644
--- a/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "CSKYFrameLowering.h"
+#include "CSKYMachineFunctionInfo.h"
#include "CSKYSubtarget.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -46,12 +47,555 @@ bool CSKYFrameLowering::hasBP(const MachineFunction &MF) const {
return MFI.hasVarSizedObjects();
}
+// Determines the size of the frame and maximum call frame size.
+void CSKYFrameLowering::determineFrameLayout(MachineFunction &MF) const {
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ const CSKYRegisterInfo *RI = STI.getRegisterInfo();
+
+ // Get the number of bytes to allocate from the FrameInfo.
+ uint64_t FrameSize = MFI.getStackSize();
+
+ // Get the alignment.
+ Align StackAlign = getStackAlign();
+ if (RI->hasStackRealignment(MF)) {
+ Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());
+ FrameSize += (MaxStackAlign.value() - StackAlign.value());
+ StackAlign = MaxStackAlign;
+ }
+
+ // Set Max Call Frame Size
+ uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign);
+ MFI.setMaxCallFrameSize(MaxCallSize);
+
+ // Make sure the frame is aligned.
+ FrameSize = alignTo(FrameSize, StackAlign);
+
+ // Update frame info.
+ MFI.setStackSize(FrameSize);
+}
+
void CSKYFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
- // FIXME: Implement this when we have function calls
+ CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ const CSKYRegisterInfo *RI = STI.getRegisterInfo();
+ const CSKYInstrInfo *TII = STI.getInstrInfo();
+ MachineBasicBlock::iterator MBBI = MBB.begin();
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+
+ Register FPReg = getFPReg(STI);
+ Register SPReg = CSKY::R14;
+ Register BPReg = getBPReg(STI);
+
+ // Debug location must be unknown since the first debug location is used
+ // to determine the end of the prologue.
+ DebugLoc DL;
+
+ if (MF.getFunction().hasFnAttribute("interrupt"))
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::NIE));
+
+ // Determine the correct frame layout
+ determineFrameLayout(MF);
+
+ // FIXME (note copied from Lanai): This appears to be overallocating. Needs
+ // investigation. Get the number of bytes to allocate from the FrameInfo.
+ uint64_t StackSize = MFI.getStackSize();
+
+ // Early exit if there is no need to allocate on the stack
+ if (StackSize == 0 && !MFI.adjustsStack())
+ return;
+
+ const auto &CSI = MFI.getCalleeSavedInfo();
+
+ unsigned spillAreaSize = CFI->getCalleeSaveAreaSize();
+
+ uint64_t ActualSize = spillAreaSize + CFI->getVarArgsSaveSize();
+
+ // First part stack allocation.
+ adjustReg(MBB, MBBI, DL, SPReg, SPReg, -(static_cast<int64_t>(ActualSize)),
+ MachineInstr::NoFlags);
+
+ // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount"
+ unsigned CFIIndex =
+ MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, ActualSize));
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex);
+
+ // The frame pointer is callee-saved, and code has been generated for us to
+ // save it to the stack. We need to skip over the storing of callee-saved
+ // registers as the frame pointer must be modified after it has been saved
+ // to the stack, not before.
+ // FIXME: assumes exactly one instruction is used to save each callee-saved
+ // register.
+ std::advance(MBBI, CSI.size());
+
+ // Iterate over list of callee-saved registers and emit .cfi_offset
+ // directives.
+ for (const auto &Entry : CSI) {
+ int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());
+ Register Reg = Entry.getReg();
+
+ unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32;
+ for (unsigned i = 0; i < Num; i++) {
+ unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
+ nullptr, RI->getDwarfRegNum(Reg, true) + i, Offset + i * 4));
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex);
+ }
+ }
+
+ // Generate new FP.
+ if (hasFP(MF)) {
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), FPReg)
+ .addReg(SPReg)
+ .setMIFlag(MachineInstr::FrameSetup);
+
+ // Emit ".cfi_def_cfa_register $fp"
+ unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
+ nullptr, RI->getDwarfRegNum(FPReg, true)));
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex);
+
+ // Second part stack allocation.
+ adjustReg(MBB, MBBI, DL, SPReg, SPReg,
+ -(static_cast<int64_t>(StackSize - ActualSize)),
+ MachineInstr::NoFlags);
+
+ // Realign Stack
+ const CSKYRegisterInfo *RI = STI.getRegisterInfo();
+ if (RI->hasStackRealignment(MF)) {
+ Align MaxAlignment = MFI.getMaxAlign();
+
+ const CSKYInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasE2() && isUInt<12>(~(-(int)MaxAlignment.value()))) {
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::ANDNI32), SPReg)
+ .addReg(SPReg)
+ .addImm(~(-(int)MaxAlignment.value()));
+ } else {
+ unsigned ShiftAmount = Log2(MaxAlignment);
+
+ if (STI.hasE2()) {
+ Register VR =
+ MF.getRegInfo().createVirtualRegister(&CSKY::GPRRegClass);
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI32), VR)
+ .addReg(SPReg)
+ .addImm(ShiftAmount);
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI32), SPReg)
+ .addReg(VR)
+ .addImm(ShiftAmount);
+ } else {
+ Register VR =
+ MF.getRegInfo().createVirtualRegister(&CSKY::mGPRRegClass);
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), VR).addReg(SPReg);
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSRI16), VR)
+ .addReg(VR)
+ .addImm(ShiftAmount);
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::LSLI16), VR)
+ .addReg(VR)
+ .addImm(ShiftAmount);
+ BuildMI(MBB, MBBI, DL, TII->get(CSKY::MOV16), SPReg).addReg(VR);
+ }
+ }
+ }
+
+ // FP will be used to restore the frame in the epilogue, so we need
+ // another base register BP to record SP after re-alignment. SP will
+ // track the current stack after allocating variable sized objects.
+ if (hasBP(MF)) {
+ // move BP, SP
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), BPReg).addReg(SPReg);
+ }
+
+ } else {
+ adjustReg(MBB, MBBI, DL, SPReg, SPReg,
+ -(static_cast<int64_t>(StackSize - ActualSize)),
+ MachineInstr::NoFlags);
+ // Emit ".cfi_def_cfa_offset StackSize"
+ unsigned CFIIndex = MF.addFrameInst(
+ MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex);
+ }
}
void CSKYFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
- // FIXME: Implement this when we have function calls
+ CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
+
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ Register FPReg = getFPReg(STI);
+ Register SPReg = CSKY::R14;
+
+ // Get the insert location for the epilogue. If there were no terminators in
+ // the block, get the last instruction.
+ MachineBasicBlock::iterator MBBI = MBB.end();
+ DebugLoc DL;
+ if (!MBB.empty()) {
+ MBBI = MBB.getFirstTerminator();
+ if (MBBI == MBB.end())
+ MBBI = MBB.getLastNonDebugInstr();
+ DL = MBBI->getDebugLoc();
+
+ // If this is not a terminator, the actual insert location should be after
+ // the last instruction.
+ if (!MBBI->isTerminator())
+ MBBI = std::next(MBBI);
+ }
+
+ const auto &CSI = MFI.getCalleeSavedInfo();
+ uint64_t StackSize = MFI.getStackSize();
+
+ uint64_t ActualSize =
+ CFI->getCalleeSaveAreaSize() + CFI->getVarArgsSaveSize();
+
+ // Skip to before the restores of callee-saved registers
+ // FIXME: assumes exactly one instruction is used to restore each
+ // callee-saved register.
+ auto LastFrameDestroy = MBBI;
+ if (!CSI.empty())
+ LastFrameDestroy = std::prev(MBBI, CSI.size());
+
+ if (hasFP(MF)) {
+ const CSKYInstrInfo *TII = STI.getInstrInfo();
+ BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::COPY), SPReg)
+ .addReg(FPReg)
+ .setMIFlag(MachineInstr::NoFlags);
+ } else {
+ adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, (StackSize - ActualSize),
+ MachineInstr::FrameDestroy);
+ }
+
+ adjustReg(MBB, MBBI, DL, SPReg, SPReg, ActualSize,
+ MachineInstr::FrameDestroy);
+}
+
+static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
+ const CSKYSubtarget &STI) {
+ unsigned Limit = (1 << 12) - 1;
+
+ for (auto &MBB : MF) {
+ for (auto &MI : MBB) {
+ if (MI.isDebugInstr())
+ continue;
+
+ for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+ if (!MI.getOperand(i).isFI())
+ continue;
+
+ if (MI.getOpcode() == CSKY::SPILL_CARRY ||
+ MI.getOpcode() == CSKY::RESTORE_CARRY ||
+ MI.getOpcode() == CSKY::STORE_PAIR ||
+ MI.getOpcode() == CSKY::LOAD_PAIR) {
+ Limit = std::min(Limit, ((1U << 12) - 1) * 4);
+ break;
+ }
+
+ if (MI.getOpcode() == CSKY::ADDI32) {
+ Limit = std::min(Limit, (1U << 12));
+ break;
+ }
+
+ if (MI.getOpcode() == CSKY::ADDI16XZ) {
+ Limit = std::min(Limit, (1U << 3));
+ break;
+ }
+
+ // ADDI16 will not require an extra register,
+ // it can reuse the destination.
+ if (MI.getOpcode() == CSKY::ADDI16)
+ break;
+
+ // Otherwise check the addressing mode.
+ switch (MI.getDesc().TSFlags & CSKYII::AddrModeMask) {
+ default:
+ LLVM_DEBUG(MI.dump());
+ llvm_unreachable(
+ "Unhandled addressing mode in stack size limit calculation");
+ case CSKYII::AddrMode32B:
+ Limit = std::min(Limit, (1U << 12) - 1);
+ break;
+ case CSKYII::AddrMode32H:
+ Limit = std::min(Limit, ((1U << 12) - 1) * 2);
+ break;
+ case CSKYII::AddrMode32WD:
+ Limit = std::min(Limit, ((1U << 12) - 1) * 4);
+ break;
+ case CSKYII::AddrMode16B:
+ Limit = std::min(Limit, (1U << 5) - 1);
+ break;
+ case CSKYII::AddrMode16H:
+ Limit = std::min(Limit, ((1U << 5) - 1) * 2);
+ break;
+ case CSKYII::AddrMode16W:
+ Limit = std::min(Limit, ((1U << 5) - 1) * 4);
+ break;
+ case CSKYII::AddrMode32SDF:
+ Limit = std::min(Limit, ((1U << 8) - 1) * 4);
+ break;
+ }
+ break; // At most one FI per instruction
+ }
+ }
+ }
+
+ return Limit;
+}
+
+void CSKYFrameLowering::determineCalleeSaves(MachineFunction &MF,
+ BitVector &SavedRegs,
+ RegScavenger *RS) const {
+ TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
+
+ CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+
+ if (hasFP(MF))
+ SavedRegs.set(CSKY::R8);
+
+ // Mark BP as used if function has dedicated base pointer.
+ if (hasBP(MF))
+ SavedRegs.set(CSKY::R7);
+
+ // If interrupt is enabled and there are calls in the handler,
+ // unconditionally save all Caller-saved registers and
+ // all FP registers, regardless whether they are used.
+ if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
+
+ static const MCPhysReg CSRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3,
+ CSKY::R12, CSKY::R13, 0};
+
+ for (unsigned i = 0; CSRegs[i]; ++i)
+ SavedRegs.set(CSRegs[i]);
+
+ if (STI.hasHighRegisters()) {
+
+ static const MCPhysReg CSHRegs[] = {CSKY::R18, CSKY::R19, CSKY::R20,
+ CSKY::R21, CSKY::R22, CSKY::R23,
+ CSKY::R24, CSKY::R25, 0};
+
+ for (unsigned i = 0; CSHRegs[i]; ++i)
+ SavedRegs.set(CSHRegs[i]);
+ }
+
+ static const MCPhysReg CSF32Regs[] = {
+ CSKY::F8_32, CSKY::F9_32, CSKY::F10_32,
+ CSKY::F11_32, CSKY::F12_32, CSKY::F13_32,
+ CSKY::F14_32, CSKY::F15_32, 0};
+ static const MCPhysReg CSF64Regs[] = {
+ CSKY::F8_64, CSKY::F9_64, CSKY::F10_64,
+ CSKY::F11_64, CSKY::F12_64, CSKY::F13_64,
+ CSKY::F14_64, CSKY::F15_64, 0};
+
+ const MCPhysReg *FRegs = NULL;
+ if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat())
+ FRegs = CSF64Regs;
+ else if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat())
+ FRegs = CSF32Regs;
+
+ if (FRegs != NULL) {
+ const MCPhysReg *Regs = MF.getRegInfo().getCalleeSavedRegs();
+
+ for (unsigned i = 0; Regs[i]; ++i)
+ if (CSKY::FPR32RegClass.contains(Regs[i]) ||
+ CSKY::FPR64RegClass.contains(Regs[i])) {
+ unsigned x = 0;
+ for (; FRegs[x]; ++x)
+ if (FRegs[x] == Regs[i])
+ break;
+ if (FRegs[x] == 0)
+ SavedRegs.set(Regs[i]);
+ }
+ }
+ }
+
+ CFI->setLRIsSpilled(SavedRegs.test(CSKY::R15));
+
+ unsigned CSStackSize = 0;
+ for (unsigned Reg : SavedRegs.set_bits()) {
+ auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;
+ CSStackSize += RegSize;
+ }
+
+ CFI->setCalleeSaveAreaSize(CSStackSize);
+
+ uint64_t Limit = estimateRSStackSizeLimit(MF, STI);
+
+ bool BigFrame = (MFI.estimateStackSize(MF) + CSStackSize >= Limit);
+
+ if (BigFrame || CFI->isCRSpilled() || !STI.hasE2()) {
+ const TargetRegisterClass *RC = &CSKY::GPRRegClass;
+ unsigned size = TRI->getSpillSize(*RC);
+ Align align = TRI->getSpillAlign(*RC);
+
+ RS->addScavengingFrameIndex(MFI.CreateStackObject(size, align, false));
+ }
+}
+
+// Not preserve stack space within prologue for outgoing variables when the
+// function contains variable size objects and let eliminateCallFramePseudoInstr
+// preserve stack space for it.
+bool CSKYFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
+ return !MF.getFrameInfo().hasVarSizedObjects();
+}
+
+bool CSKYFrameLowering::spillCalleeSavedRegisters(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+ ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
+ if (CSI.empty())
+ return true;
+
+ MachineFunction *MF = MBB.getParent();
+ const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
+ DebugLoc DL;
+ if (MI != MBB.end() && !MI->isDebugInstr())
+ DL = MI->getDebugLoc();
+
+ for (auto &CS : CSI) {
+ // Insert the spill to the stack frame.
+ Register Reg = CS.getReg();
+ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
+ TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);
+ }
+
+ return true;
+}
+
+bool CSKYFrameLowering::restoreCalleeSavedRegisters(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+ MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
+ if (CSI.empty())
+ return true;
+
+ MachineFunction *MF = MBB.getParent();
+ const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
+ DebugLoc DL;
+ if (MI != MBB.end() && !MI->isDebugInstr())
+ DL = MI->getDebugLoc();
+
+ for (auto &CS : reverse(CSI)) {
+ Register Reg = CS.getReg();
+ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
+ TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);
+ assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
+ }
+
+ return true;
+}
+
+// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
+MachineBasicBlock::iterator CSKYFrameLowering::eliminateCallFramePseudoInstr(
+ MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+ Register SPReg = CSKY::R14;
+ DebugLoc DL = MI->getDebugLoc();
+
+ if (!hasReservedCallFrame(MF)) {
+ // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
+ // ADJCALLSTACKUP must be converted to instructions manipulating the stack
+ // pointer. This is necessary when there is a variable length stack
+ // allocation (e.g. alloca), which means it's not possible to allocate
+ // space for outgoing arguments from within the function prologue.
+ int64_t Amount = MI->getOperand(0).getImm();
+
+ if (Amount != 0) {
+ // Ensure the stack remains aligned after adjustment.
+ Amount = alignSPAdjust(Amount);
+
+ if (MI->getOpcode() == CSKY::ADJCALLSTACKDOWN)
+ Amount = -Amount;
+
+ adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
+ }
+ }
+
+ return MBB.erase(MI);
+}
+
+void CSKYFrameLowering::adjustReg(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register DestReg,
+ Register SrcReg, int64_t Val,
+ MachineInstr::MIFlag Flag) const {
+ const CSKYInstrInfo *TII = STI.getInstrInfo();
+
+ if (DestReg == SrcReg && Val == 0)
+ return;
+
+ // TODO: Add 16-bit instruction support with immediate num
+ if (STI.hasE2() && isUInt<12>(std::abs(Val) - 1)) {
+ BuildMI(MBB, MBBI, DL, TII->get(Val < 0 ? CSKY::SUBI32 : CSKY::ADDI32),
+ DestReg)
+ .addReg(SrcReg)
+ .addImm(std::abs(Val))
+ .setMIFlag(Flag);
+ } else if (!STI.hasE2() && isShiftedUInt<7, 2>(std::abs(Val))) {
+ BuildMI(MBB, MBBI, DL,
+ TII->get(Val < 0 ? CSKY::SUBI16SPSP : CSKY::ADDI16SPSP), CSKY::R14)
+ .addReg(CSKY::R14, RegState::Kill)
+ .addImm(std::abs(Val))
+ .setMIFlag(Flag);
+ } else {
+
+ unsigned Op = 0;
+
+ if (STI.hasE2()) {
+ Op = Val < 0 ? CSKY::SUBU32 : CSKY::ADDU32;
+ } else {
+ assert(SrcReg == DestReg);
+ Op = Val < 0 ? CSKY::SUBU16XZ : CSKY::ADDU16XZ;
+ }
+
+ Register ScratchReg = TII->movImm(MBB, MBBI, DL, std::abs(Val), Flag);
+
+ BuildMI(MBB, MBBI, DL, TII->get(Op), DestReg)
+ .addReg(SrcReg)
+ .addReg(ScratchReg, RegState::Kill)
+ .setMIFlag(Flag);
+ }
+}
+
+StackOffset
+CSKYFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
+ Register &FrameReg) const {
+ const CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
+ const auto &CSI = MFI.getCalleeSavedInfo();
+
+ int MinCSFI = 0;
+ int MaxCSFI = -1;
+
+ int Offset = MFI.getObjectOffset(FI) + MFI.getOffsetAdjustment();
+
+ if (CSI.size()) {
+ MinCSFI = CSI[0].getFrameIdx();
+ MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
+ }
+
+ if (FI >= MinCSFI && FI <= MaxCSFI) {
+ FrameReg = CSKY::R14;
+ Offset += CFI->getVarArgsSaveSize() + CFI->getCalleeSaveAreaSize();
+ } else if (RI->hasStackRealignment(MF)) {
+ assert(hasFP(MF));
+ if (!MFI.isFixedObjectIndex(FI)) {
+ FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14;
+ Offset += MFI.getStackSize();
+ } else {
+ FrameReg = getFPReg(STI);
+ Offset += CFI->getVarArgsSaveSize() + CFI->getCalleeSaveAreaSize();
+ }
+ } else {
+ if (MFI.isFixedObjectIndex(FI) && hasFP(MF)) {
+ FrameReg = getFPReg(STI);
+ Offset += CFI->getVarArgsSaveSize() + CFI->getCalleeSaveAreaSize();
+ } else {
+ FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14;
+ Offset += MFI.getStackSize();
+ }
+ }
+
+ return StackOffset::getFixed(Offset);
}
diff --git a/llvm/lib/Target/CSKY/CSKYFrameLowering.h b/llvm/lib/Target/CSKY/CSKYFrameLowering.h
index 49921a1866bce..69bf01cf1801e 100644
--- a/llvm/lib/Target/CSKY/CSKYFrameLowering.h
+++ b/llvm/lib/Target/CSKY/CSKYFrameLowering.h
@@ -21,6 +21,11 @@ class CSKYSubtarget;
class CSKYFrameLowering : public TargetFrameLowering {
const CSKYSubtarget &STI;
+ void determineFrameLayout(MachineFunction &MF) const;
+ void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ const DebugLoc &DL, Register DestReg, Register SrcReg,
+ int64_t Val, MachineInstr::MIFlag Flag) const;
+
public:
explicit CSKYFrameLowering(const CSKYSubtarget &STI)
: TargetFrameLowering(StackGrowsDown,
@@ -31,8 +36,39 @@ class CSKYFrameLowering : public TargetFrameLowering {
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
+ StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
+ Register &FrameReg) const override;
+
+ void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
+ RegScavenger *RS) const override;
+
+ bool assignCalleeSavedSpillSlots(
+ MachineFunction &MF, const TargetRegisterInfo *TRI,
+ std::vector<CalleeSavedInfo> &CSI) const override {
+
+ std::reverse(CSI.begin(), CSI.end());
+
+ return false;
+ }
+
+ bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ ArrayRef<CalleeSavedInfo> CSI,
+ const TargetRegisterInfo *TRI) const override;
+ bool
+ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI,
+ MutableArrayRef<CalleeSavedInfo> CSI,
+ const TargetRegisterInfo *TRI) const override;
+
bool hasFP(const MachineFunction &MF) const override;
bool hasBP(const MachineFunction &MF) const;
+
+ bool hasReservedCallFrame(const MachineFunction &MF) const override;
+
+ MachineBasicBlock::iterator
+ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const override;
};
} // namespace llvm
#endif
diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
index 8dc91904b8cc1..a01f061387287 100644
--- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
@@ -68,6 +68,17 @@ void CSKYDAGToDAGISel::Select(SDNode *N) {
case ISD::SUBCARRY:
IsSelected = selectSubCarry(N);
break;
+ case ISD::FrameIndex: {
+ SDValue Imm = CurDAG->getTargetConstant(0, Dl, MVT::i32);
+ int FI = cast<FrameIndexSDNode>(N)->getIndex();
+ SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
+ ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32
+ : CSKY::ADDI16XZ,
+ Dl, MVT::i32, TFI, Imm));
+
+ IsSelected = true;
+ break;
+ }
}
if (IsSelected)
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index a1f7cc685d4c6..214ed7ff54ee5 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -53,6 +53,9 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
+ setOperationAction(ISD::BR_CC, MVT::i32, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
index 6fcb136cd99b2..a92f69da86cd1 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
@@ -26,6 +26,195 @@ CSKYInstrInfo::CSKYInstrInfo(CSKYSubtarget &STI)
: CSKYGenInstrInfo(CSKY::ADJCALLSTACKDOWN, CSKY::ADJCALLSTACKUP), STI(STI) {
}
+static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
+ SmallVectorImpl<MachineOperand> &Cond) {
+ // Block ends with fall-through condbranch.
+ assert(LastInst.getDesc().isConditionalBranch() &&
+ "Unknown conditional branch");
+ Target = LastInst.getOperand(1).getMBB();
+ Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
+ Cond.push_back(LastInst.getOperand(0));
+}
+
+bool CSKYInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
+ MachineBasicBlock *&TBB,
+ MachineBasicBlock *&FBB,
+ SmallVectorImpl<MachineOperand> &Cond,
+ bool AllowModify) const {
+ TBB = FBB = nullptr;
+ Cond.clear();
+
+ // If the block has no terminators, it just falls into the block after it.
+ MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
+ if (I == MBB.end() || !isUnpredicatedTerminator(*I))
+ return false;
+
+ // Count the number of terminators and find the first unconditional or
+ // indirect branch.
+ MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
+ int NumTerminators = 0;
+ for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
+ J++) {
+ NumTerminators++;
+ if (J->getDesc().isUnconditionalBranch() ||
+ J->getDesc().isIndirectBranch()) {
+ FirstUncondOrIndirectBr = J.getReverse();
+ }
+ }
+
+ // If AllowModify is true, we can erase any terminators after
+ // FirstUncondOrIndirectBR.
+ if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
+ while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
+ std::next(FirstUncondOrIndirectBr)->eraseFromParent();
+ NumTerminators--;
+ }
+ I = FirstUncondOrIndirectBr;
+ }
+
+ // We can't handle blocks that end in an indirect branch.
+ if (I->getDesc().isIndirectBranch())
+ return true;
+
+ // We can't handle blocks with more than 2 terminators.
+ if (NumTerminators > 2)
+ return true;
+
+ // Handle a single unconditional branch.
+ if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
+ TBB = getBranchDestBlock(*I);
+ return false;
+ }
+
+ // Handle a single conditional branch.
+ if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
+ parseCondBranch(*I, TBB, Cond);
+ return false;
+ }
+
+ // Handle a conditional branch followed by an unconditional branch.
+ if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
+ I->getDesc().isUnconditionalBranch()) {
+ parseCondBranch(*std::prev(I), TBB, Cond);
+ FBB = getBranchDestBlock(*I);
+ return false;
+ }
+
+ // Otherwise, we can't handle this.
+ return true;
+}
+
+unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB,
+ int *BytesRemoved) const {
+ if (BytesRemoved)
+ *BytesRemoved = 0;
+ MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
+ if (I == MBB.end())
+ return 0;
+
+ if (!I->getDesc().isUnconditionalBranch() &&
+ !I->getDesc().isConditionalBranch())
+ return 0;
+
+ // Remove the branch.
+ if (BytesRemoved)
+ *BytesRemoved += getInstSizeInBytes(*I);
+ I->eraseFromParent();
+
+ I = MBB.end();
+
+ if (I == MBB.begin())
+ return 1;
+ --I;
+ if (!I->getDesc().isConditionalBranch())
+ return 1;
+
+ // Remove the branch.
+ if (BytesRemoved)
+ *BytesRemoved += getInstSizeInBytes(*I);
+ I->eraseFromParent();
+ return 2;
+}
+
+MachineBasicBlock *
+CSKYInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
+ assert(MI.getDesc().isBranch() && "Unexpected opcode!");
+ // The branch target is always the last operand.
+ int NumOp = MI.getNumExplicitOperands();
+ assert(MI.getOperand(NumOp - 1).isMBB() && "Expected MBB!");
+ return MI.getOperand(NumOp - 1).getMBB();
+}
+
+unsigned CSKYInstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
+ if (BytesAdded)
+ *BytesAdded = 0;
+
+ // Shouldn't be a fall through.
+ assert(TBB && "insertBranch must not be told to insert a fallthrough");
+ assert((Cond.size() == 2 || Cond.size() == 0) &&
+ "CSKY branch conditions have two components!");
+
+ // Unconditional branch.
+ if (Cond.empty()) {
+ MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB);
+ if (BytesAdded)
+ *BytesAdded += getInstSizeInBytes(MI);
+ return 1;
+ }
+
+ // Either a one or two-way conditional branch.
+ unsigned Opc = Cond[0].getImm();
+ MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB);
+ if (BytesAdded)
+ *BytesAdded += getInstSizeInBytes(CondMI);
+
+ // One-way conditional branch.
+ if (!FBB)
+ return 1;
+
+ // Two-way conditional branch.
+ MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB);
+ if (BytesAdded)
+ *BytesAdded += getInstSizeInBytes(MI);
+ return 2;
+}
+
+static unsigned getOppositeBranchOpc(unsigned Opcode) {
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unknown conditional branch!");
+ case CSKY::BT32:
+ return CSKY::BF32;
+ case CSKY::BT16:
+ return CSKY::BF16;
+ case CSKY::BF32:
+ return CSKY::BT32;
+ case CSKY::BF16:
+ return CSKY::BT16;
+ case CSKY::BHZ32:
+ return CSKY::BLSZ32;
+ case CSKY::BHSZ32:
+ return CSKY::BLZ32;
+ case CSKY::BLZ32:
+ return CSKY::BHSZ32;
+ case CSKY::BLSZ32:
+ return CSKY::BHZ32;
+ case CSKY::BNEZ32:
+ return CSKY::BEZ32;
+ case CSKY::BEZ32:
+ return CSKY::BNEZ32;
+ }
+}
+
+bool CSKYInstrInfo::reverseBranchCondition(
+ SmallVectorImpl<MachineOperand> &Cond) const {
+ assert((Cond.size() == 2) && "Invalid branch condition!");
+ Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
+ return false;
+}
+
Register CSKYInstrInfo::movImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, int64_t Val,
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
index 450641d96b74c..d061cf24a9885 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
@@ -50,6 +50,24 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
+ unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+ MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
+ const DebugLoc &DL,
+ int *BytesAdded = nullptr) const override;
+
+ bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
+ MachineBasicBlock *&FBB,
+ SmallVectorImpl<MachineOperand> &Cond,
+ bool AllowModify = false) const override;
+
+ unsigned removeBranch(MachineBasicBlock &MBB,
+ int *BytesRemoved = nullptr) const override;
+
+ bool
+ reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
+
+ MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
+
// Materializes the given integer Val into DstReg.
Register movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, int64_t Val,
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index 30d9206eec68d..6c95f13c06b06 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -1057,6 +1057,153 @@ let Predicates = [iHas2E3] in {
def : Pat<(and GPR:$src, 65535), (ZEXT32 GPR:$src, 15, 0)>;
}
+// Branch Patterns.
+let Predicates = [iHasE2] in {
+ def : Pat<(brcond CARRY:$ca, bb:$imm16),
+ (BT32 CARRY:$ca, bb:$imm16)>;
+
+ def : Pat<(brcond (i32 (setne GPR:$rs1, uimm16:$rs2)), bb:$imm16),
+ (BT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), bb:$imm16)>;
+ def : Pat<(brcond (i32 (seteq GPR:$rs1, uimm16:$rs2)), bb:$imm16),
+ (BF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), bb:$imm16)>;
+ def : Pat<(brcond (i32 (setuge GPR:$rs1, oimm16:$rs2)), bb:$imm16),
+ (BT32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
+ def : Pat<(brcond (i32 (setult GPR:$rs1, oimm16:$rs2)), bb:$imm16),
+ (BF32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
+ def : Pat<(brcond (i32 (setlt GPR:$rs1, oimm16:$rs2)), bb:$imm16),
+ (BT32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
+ def : Pat<(brcond (i32 (setge GPR:$rs1, oimm16:$rs2)), bb:$imm16),
+ (BF32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
+
+}
+
+let Predicates = [iHas2E3] in {
+
+def : Pat<(brcond (i32 (setne GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BT32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
+def : Pat<(brcond (i32 (seteq GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BF32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
+def : Pat<(brcond (i32 (setuge GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BT32 (CMPHS32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
+def : Pat<(brcond (i32 (setule GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BT32 (CMPHS32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
+def : Pat<(brcond (i32 (setult GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BF32 (CMPHS32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
+def : Pat<(brcond (i32 (setugt GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BF32 (CMPHS32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
+def : Pat<(brcond (i32 (setlt GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BT32 (CMPLT32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
+def : Pat<(brcond (i32 (setgt GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BT32 (CMPLT32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
+def : Pat<(brcond (i32 (setge GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BF32 (CMPLT32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
+def : Pat<(brcond (i32 (setle GPR:$rs1, GPR:$rs2)), bb:$imm16),
+ (BF32 (CMPLT32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
+
+def : Pat<(brcond (i32 (seteq GPR:$rs1, (i32 0))), bb:$imm16),
+ (BEZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setne GPR:$rs1, (i32 0))), bb:$imm16),
+ (BNEZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setlt GPR:$rs1, (i32 0))), bb:$imm16),
+ (BLZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 0))), bb:$imm16),
+ (BHSZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setgt GPR:$rs1, (i32 0))), bb:$imm16),
+ (BHZ32 GPR:$rs1, bb:$imm16)>;
+def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 0))), bb:$imm16),
+ (BLSZ32 GPR:$rs1, bb:$imm16)>;
+}
+
+// Compare Patterns.
+let Predicates = [iHas2E3] in {
+ def : Pat<(setne GPR:$rs1, GPR:$rs2),
+ (CMPNE32 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(i32 (seteq GPR:$rs1, GPR:$rs2)),
+ (MVCV32 (CMPNE32 GPR:$rs1, GPR:$rs2))>;
+ def : Pat<(setuge GPR:$rs1, GPR:$rs2),
+ (CMPHS32 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(setule GPR:$rs1, GPR:$rs2),
+ (CMPHS32 GPR:$rs2, GPR:$rs1)>;
+ def : Pat<(i32 (setult GPR:$rs1, GPR:$rs2)),
+ (MVCV32 (CMPHS32 GPR:$rs1, GPR:$rs2))>;
+ def : Pat<(i32 (setugt GPR:$rs1, GPR:$rs2)),
+ (MVCV32 (CMPHS32 GPR:$rs2, GPR:$rs1))>;
+ def : Pat<(setlt GPR:$rs1, GPR:$rs2),
+ (CMPLT32 GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(setgt GPR:$rs1, GPR:$rs2),
+ (CMPLT32 GPR:$rs2, GPR:$rs1)>;
+ def : Pat<(i32 (setge GPR:$rs1, GPR:$rs2)),
+ (MVCV32 (CMPLT32 GPR:$rs1, GPR:$rs2))>;
+ def : Pat<(i32 (setle GPR:$rs1, GPR:$rs2)),
+ (MVCV32 (CMPLT32 GPR:$rs2, GPR:$rs1))>;
+}
+
+let Predicates = [iHasE2] in {
+ def : Pat<(setne GPR:$rs1, uimm16:$rs2),
+ (CMPNEI32 GPR:$rs1, uimm16:$rs2)>;
+ let Predicates = [iHas2E3] in
+ def : Pat<(i32 (seteq GPR:$rs1, uimm16:$rs2)),
+ (MVCV32 (CMPNEI32 GPR:$rs1, uimm16:$rs2))>;
+ def : Pat<(setuge GPR:$rs1, oimm16:$rs2),
+ (CMPHSI32 GPR:$rs1, oimm16:$rs2)>;
+ let Predicates = [iHas2E3] in
+ def : Pat<(i32 (setult GPR:$rs1, oimm16:$rs2)),
+ (MVCV32 (CMPHSI32 GPR:$rs1, oimm16:$rs2))>;
+ def : Pat<(setlt GPR:$rs1, oimm16:$rs2),
+ (CMPLTI32 GPR:$rs1, oimm16:$rs2)>;
+ let Predicates = [iHas2E3] in
+ def : Pat<(i32 (setge GPR:$rs1, oimm16:$rs2)),
+ (MVCV32 (CMPLTI32 GPR:$rs1, oimm16:$rs2))>;
+}
+
+// Select Patterns.
+let Predicates = [iHasE2] in {
+def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
+ (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;
+def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
+ (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;
+
+def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$rx, GPR:$false)>;
+
+def : Pat<(select (i32 (setuge GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPHS32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setuge GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setule GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPHS32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setult GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPHS32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setult GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setugt GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPHS32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
+
+def : Pat<(select (i32 (setlt GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPLT32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setlt GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setgt GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVT32 (CMPLT32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setge GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPLT32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setge GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
+def : Pat<(select (i32 (setle GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
+ (MOVF32 (CMPLT32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
+
+def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
+ (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
+def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
+ (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
+}
+
// Constant materialize patterns.
let Predicates = [iHasE2] in
def : Pat<(i32 imm:$imm),
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
index 668247bbbd87f..543f2e3d43d4d 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
@@ -22,4 +22,6 @@ CSKYMCAsmInfo::CSKYMCAsmInfo(const Triple &TargetTriple) {
AlignmentIsInBytes = false;
SupportsDebugInformation = true;
CommentString = "#";
+
+ ExceptionsType = ExceptionHandling::DwarfCFI;
}
diff --git a/llvm/test/CodeGen/CSKY/br.ll b/llvm/test/CodeGen/CSKY/br.ll
new file mode 100644
index 0000000000000..2dfb0306da473
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/br.ll
@@ -0,0 +1,3650 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
+
+;EQ
+define i32 @brRR_eq(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bt32 .LBB0_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB0_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_eq(i32 %x) {
+; CHECK-LABEL: brRI_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: bt32 .LBB1_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB1_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_eq(i32 %x) {
+; CHECK-LABEL: brR0_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: bez32 a0, .LBB2_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB2_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;NE
+define i32 @brRR_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bf32 .LBB3_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB3_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ne(i32 %x) {
+; CHECK-LABEL: brRI_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: bf32 .LBB4_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB4_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ne(i32 %x) {
+; CHECK-LABEL: brR0_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: bez32 a0, .LBB5_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB5_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UGT
+define i32 @brRR_ugt(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bt32 .LBB6_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB6_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ugt(i32 %x) {
+; CHECK-LABEL: brRI_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: bf32 .LBB7_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB7_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ugt(i32 %x) {
+; CHECK-LABEL: brR0_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: bez32 a0, .LBB8_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB8_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UGE
+define i32 @brRR_uge(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB9_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB9_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_uge(i32 %x) {
+; CHECK-LABEL: brRI_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: bf32 .LBB10_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB10_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;ULT
+define i32 @brRR_ult(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bt32 .LBB11_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB11_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ult(i32 %x) {
+; CHECK-LABEL: brRI_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB12_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB12_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+
+;ULE
+define i32 @brRR_ule(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bf32 .LBB13_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB13_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ule(i32 %x) {
+; CHECK-LABEL: brRI_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB14_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB14_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ule(i32 %x) {
+; CHECK-LABEL: brR0_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: bnez32 a0, .LBB15_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB15_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SGT
+define i32 @brRR_sgt(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bf32 .LBB16_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB16_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_sgt(i32 %x) {
+; CHECK-LABEL: brRI_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplti16 a0, 11
+; CHECK-NEXT: bt32 .LBB17_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB17_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_sgt(i32 %x) {
+; CHECK-LABEL: brR0_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplti16 a0, 1
+; CHECK-NEXT: bt32 .LBB18_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB18_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SGE
+define i32 @brRR_sge(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB19_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB19_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_sge(i32 %x) {
+; CHECK-LABEL: brRI_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplti16 a0, 10
+; CHECK-NEXT: bt32 .LBB20_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB20_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_sge(i32 %x) {
+; CHECK-LABEL: brR0_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: blz32 a0, .LBB21_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB21_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SLT
+define i32 @brRR_slt(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bf32 .LBB22_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB22_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_slt(i32 %x) {
+; CHECK-LABEL: brRI_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB23_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB23_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_slt(i32 %x) {
+; CHECK-LABEL: brR0_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 65535
+; CHECK-NEXT: ori32 a1, a1, 65535
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bf32 .LBB24_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB24_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SLE
+define i32 @brRR_sle(i32 %x, i32 %y) {
+; CHECK-LABEL: brRR_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bt32 .LBB25_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB25_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i32 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_sle(i32 %x) {
+; CHECK-LABEL: brRI_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB26_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB26_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i32 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_sle(i32 %x) {
+; CHECK-LABEL: brR0_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: bhz32 a0, .LBB27_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB27_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i32 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+
+define i32 @brCBit(i1 %c) {
+; CHECK-LABEL: brCBit:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB28_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB28_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ br i1 %c, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+
+;EQ
+define i64 @brRR_i64_eq(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a1, a3
+; CHECK-NEXT: xor16 a0, a2
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bnez32 a0, .LBB29_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB29_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_eq(i64 %x) {
+; CHECK-LABEL: brR0_i64_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 10
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bnez32 a0, .LBB30_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB30_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_eq(i64 %x) {
+; CHECK-LABEL: brRI_i64_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bez32 a0, .LBB31_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB31_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;NE
+define i64 @brRR_i64_ne(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a1, a3
+; CHECK-NEXT: xor16 a0, a2
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bez32 a0, .LBB32_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB32_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_ne(i64 %x) {
+; CHECK-LABEL: brRI_i64_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 10
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bez32 a0, .LBB33_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB33_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_ne(i64 %x) {
+; CHECK-LABEL: brR0_i64_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bez32 a0, .LBB34_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB34_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;UGT
+define i64 @brRR_i64_ugt(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: cmphs16 a1, a3
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 12)
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a1, (sp, 12)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB35_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB35_2
+; CHECK-NEXT: .LBB35_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB35_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_ugt(i64 %x) {
+; CHECK-LABEL: brRI_i64_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB36_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB36_2
+; CHECK-NEXT: .LBB36_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB36_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_ugt(i64 %x) {
+; CHECK-LABEL: brR0_i64_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bez32 a0, .LBB37_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB37_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;UGE
+define i64 @brRR_i64_uge(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmphs16 a3, a1
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB38_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB38_2
+; CHECK-NEXT: .LBB38_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB38_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_uge(i64 %x) {
+; CHECK-LABEL: brRI_i64_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB39_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB39_2
+; CHECK-NEXT: .LBB39_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB39_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;ULT
+define i64 @brRR_i64_ult(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: cmphs16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 12)
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a1, (sp, 12)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB40_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB40_2
+; CHECK-NEXT: .LBB40_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB40_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_ult(i64 %x) {
+; CHECK-LABEL: brRI_i64_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a2, 9
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB41_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB41_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+
+;ULE
+define i64 @brRR_i64_ule(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmphs16 a1, a3
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB42_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB42_2
+; CHECK-NEXT: .LBB42_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB42_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_ule(i64 %x) {
+; CHECK-LABEL: brRI_i64_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a2, 10
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB43_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB43_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_ule(i64 %x) {
+; CHECK-LABEL: brR0_i64_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: bnez32 a0, .LBB44_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB44_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;SGT
+define i64 @brRR_i64_sgt(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: cmplt16 a1, a3
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB45_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB45_2
+; CHECK-NEXT: .LBB45_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB45_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_sgt(i64 %x) {
+; CHECK-LABEL: brRI_i64_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a1, a2
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB46_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB46_2
+; CHECK-NEXT: .LBB46_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB46_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_sgt(i64 %x) {
+; CHECK-LABEL: brR0_i64_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a1, a2
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB47_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB47_2
+; CHECK-NEXT: .LBB47_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB47_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;SGE
+define i64 @brRR_i64_sge(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmplt16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB48_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB48_2
+; CHECK-NEXT: .LBB48_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB48_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_sge(i64 %x) {
+; CHECK-LABEL: brRI_i64_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a1, a2
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB49_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB49_2
+; CHECK-NEXT: .LBB49_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB49_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_sge(i64 %x) {
+; CHECK-LABEL: brR0_i64_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: blz32 a1, .LBB50_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB50_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;SLT
+define i64 @brRR_i64_slt(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: cmplt16 a3, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB51_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB51_2
+; CHECK-NEXT: .LBB51_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB51_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_slt(i64 %x) {
+; CHECK-LABEL: brRI_i64_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a2, a1
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 8)
+; CHECK-NEXT: movi16 a2, 9
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB52_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB52_2
+; CHECK-NEXT: .LBB52_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB52_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_slt(i64 %x) {
+; CHECK-LABEL: brR0_i64_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a0, 65535
+; CHECK-NEXT: ori32 a0, a0, 65535
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bf32 .LBB53_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB53_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+;SLE
+define i64 @brRR_i64_sle(i64 %x, i64 %y) {
+; CHECK-LABEL: brRR_i64_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmplt16 a1, a3
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB54_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB54_2
+; CHECK-NEXT: .LBB54_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB54_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i64 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brRI_i64_sle(i64 %x) {
+; CHECK-LABEL: brRI_i64_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a2, a1
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 8)
+; CHECK-NEXT: movi16 a2, 10
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB55_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB55_2
+; CHECK-NEXT: .LBB55_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB55_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i64 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+define i64 @brR0_i64_sle(i64 %x) {
+; CHECK-LABEL: brR0_i64_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a2, a1
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 12)
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a1, (sp, 12)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: bt32 .LBB56_3
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: br32 .LBB56_2
+; CHECK-NEXT: .LBB56_3: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: .LBB56_2: # %label1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i64 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+
+define i64 @brCBit_i64(i1 %c) {
+; CHECK-LABEL: brCBit_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB57_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB57_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: rts16
+entry:
+ br i1 %c, label %label1, label %label2
+label1:
+ ret i64 1
+label2:
+ ret i64 0
+}
+
+
+;EQ
+define i16 @brRR_i16_eq(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bt32 .LBB58_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB58_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_eq(i16 %x) {
+; CHECK-LABEL: brRI_i16_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: bt32 .LBB59_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB59_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_eq(i16 %x) {
+; CHECK-LABEL: brR0_i16_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: bez32 a0, .LBB60_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB60_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;NE
+define i16 @brRR_i16_ne(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bf32 .LBB61_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB61_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_ne(i16 %x) {
+; CHECK-LABEL: brRI_i16_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: bf32 .LBB62_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB62_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_ne(i16 %x) {
+; CHECK-LABEL: brR0_i16_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: bez32 a0, .LBB63_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB63_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;UGT
+define i16 @brRR_i16_ugt(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bt32 .LBB64_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB64_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_ugt(i16 %x) {
+; CHECK-LABEL: brRI_i16_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: bf32 .LBB65_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB65_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_ugt(i16 %x) {
+; CHECK-LABEL: brR0_i16_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: bez32 a0, .LBB66_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB66_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;UGE
+define i16 @brRR_i16_uge(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB67_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB67_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_uge(i16 %x) {
+; CHECK-LABEL: brRI_i16_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: bf32 .LBB68_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB68_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;ULT
+define i16 @brRR_i16_ult(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bt32 .LBB69_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB69_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_ult(i16 %x) {
+; CHECK-LABEL: brRI_i16_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB70_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB70_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+
+;ULE
+define i16 @brRR_i16_ule(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bf32 .LBB71_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB71_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_ule(i16 %x) {
+; CHECK-LABEL: brRI_i16_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB72_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB72_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_ule(i16 %x) {
+; CHECK-LABEL: brR0_i16_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: bnez32 a0, .LBB73_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB73_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;SGT
+define i16 @brRR_i16_sgt(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bf32 .LBB74_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB74_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_sgt(i16 %x) {
+; CHECK-LABEL: brRI_i16_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 11
+; CHECK-NEXT: bt32 .LBB75_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB75_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_sgt(i16 %x) {
+; CHECK-LABEL: brR0_i16_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 1
+; CHECK-NEXT: bt32 .LBB76_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB76_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;SGE
+define i16 @brRR_i16_sge(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB77_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB77_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_sge(i16 %x) {
+; CHECK-LABEL: brRI_i16_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 10
+; CHECK-NEXT: bt32 .LBB78_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB78_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_sge(i16 %x) {
+; CHECK-LABEL: brR0_i16_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: blz32 a0, .LBB79_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB79_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;SLT
+define i16 @brRR_i16_slt(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bf32 .LBB80_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB80_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_slt(i16 %x) {
+; CHECK-LABEL: brRI_i16_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB81_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB81_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_slt(i16 %x) {
+; CHECK-LABEL: brR0_i16_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movih32 a1, 65535
+; CHECK-NEXT: ori32 a1, a1, 65535
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bf32 .LBB82_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB82_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+;SLE
+define i16 @brRR_i16_sle(i16 %x, i16 %y) {
+; CHECK-LABEL: brRR_i16_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bt32 .LBB83_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB83_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i16 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brRI_i16_sle(i16 %x) {
+; CHECK-LABEL: brRI_i16_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB84_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB84_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i16 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+define i16 @brR0_i16_sle(i16 %x) {
+; CHECK-LABEL: brR0_i16_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: bhz32 a0, .LBB85_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB85_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i16 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+
+define i16 @brCBit_i16(i1 %c) {
+; CHECK-LABEL: brCBit_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB86_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB86_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ br i1 %c, label %label1, label %label2
+label1:
+ ret i16 1
+label2:
+ ret i16 0
+}
+
+
+;EQ
+define i8 @brRR_i8_eq(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bt32 .LBB87_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB87_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_eq(i8 %x) {
+; CHECK-LABEL: brRI_i8_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: bt32 .LBB88_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB88_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_eq(i8 %x) {
+; CHECK-LABEL: brR0_i8_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: bez32 a0, .LBB89_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB89_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;NE
+define i8 @brRR_i8_ne(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bf32 .LBB90_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB90_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_ne(i8 %x) {
+; CHECK-LABEL: brRI_i8_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: bf32 .LBB91_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB91_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_ne(i8 %x) {
+; CHECK-LABEL: brR0_i8_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: bez32 a0, .LBB92_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB92_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;UGT
+define i8 @brRR_i8_ugt(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bt32 .LBB93_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB93_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_ugt(i8 %x) {
+; CHECK-LABEL: brRI_i8_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: bf32 .LBB94_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB94_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_ugt(i8 %x) {
+; CHECK-LABEL: brR0_i8_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: bez32 a0, .LBB95_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB95_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;UGE
+define i8 @brRR_i8_uge(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB96_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB96_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_uge(i8 %x) {
+; CHECK-LABEL: brRI_i8_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: bf32 .LBB97_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB97_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;ULT
+define i8 @brRR_i8_ult(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bt32 .LBB98_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB98_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_ult(i8 %x) {
+; CHECK-LABEL: brRI_i8_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB99_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB99_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+
+;ULE
+define i8 @brRR_i8_ule(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bf32 .LBB100_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB100_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_ule(i8 %x) {
+; CHECK-LABEL: brRI_i8_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB101_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB101_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_ule(i8 %x) {
+; CHECK-LABEL: brR0_i8_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: bnez32 a0, .LBB102_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB102_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;SGT
+define i8 @brRR_i8_sgt(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bf32 .LBB103_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB103_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_sgt(i8 %x) {
+; CHECK-LABEL: brRI_i8_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 11
+; CHECK-NEXT: bt32 .LBB104_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB104_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_sgt(i8 %x) {
+; CHECK-LABEL: brR0_i8_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 1
+; CHECK-NEXT: bt32 .LBB105_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB105_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;SGE
+define i8 @brRR_i8_sge(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB106_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB106_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_sge(i8 %x) {
+; CHECK-LABEL: brRI_i8_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 10
+; CHECK-NEXT: bt32 .LBB107_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB107_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_sge(i8 %x) {
+; CHECK-LABEL: brR0_i8_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: blz32 a0, .LBB108_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB108_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;SLT
+define i8 @brRR_i8_slt(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bf32 .LBB109_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB109_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_slt(i8 %x) {
+; CHECK-LABEL: brRI_i8_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB110_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB110_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_slt(i8 %x) {
+; CHECK-LABEL: brR0_i8_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movih32 a1, 65535
+; CHECK-NEXT: ori32 a1, a1, 65535
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bf32 .LBB111_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB111_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+;SLE
+define i8 @brRR_i8_sle(i8 %x, i8 %y) {
+; CHECK-LABEL: brRR_i8_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bt32 .LBB112_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB112_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i8 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brRI_i8_sle(i8 %x) {
+; CHECK-LABEL: brRI_i8_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB113_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB113_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i8 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+define i8 @brR0_i8_sle(i8 %x) {
+; CHECK-LABEL: brR0_i8_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: bhz32 a0, .LBB114_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB114_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i8 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+
+define i8 @brCBit_i8(i1 %c) {
+; CHECK-LABEL: brCBit_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB115_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB115_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ br i1 %c, label %label1, label %label2
+label1:
+ ret i8 1
+label2:
+ ret i8 0
+}
+
+
+;EQ
+define i1 @brRR_i1_eq(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: andi32 a1, a1, 1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bt32 .LBB116_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB116_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_eq(i1 %x) {
+; CHECK-LABEL: brRI_i1_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB117_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB117_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_eq(i1 %x) {
+; CHECK-LABEL: brR0_i1_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB118_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB118_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;NE
+define i1 @brRR_i1_ne(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: andi32 a1, a1, 1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: bf32 .LBB119_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB119_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_ne(i1 %x) {
+; CHECK-LABEL: brRI_i1_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB120_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB120_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_ne(i1 %x) {
+; CHECK-LABEL: brR0_i1_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB121_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB121_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;UGT
+define i1 @brRR_i1_ugt(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a1, a1, 1
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bt32 .LBB122_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB122_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_ugt(i1 %x) {
+; CHECK-LABEL: brRI_i1_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB123_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB123_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_ugt(i1 %x) {
+; CHECK-LABEL: brR0_i1_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB124_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB124_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ugt i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;UGE
+define i1 @brRR_i1_uge(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: andi32 a1, a1, 1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bf32 .LBB125_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB125_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_uge(i1 %x) {
+; CHECK-LABEL: brRI_i1_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB126_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB126_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp uge i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;ULT
+define i1 @brRR_i1_ult(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: andi32 a1, a1, 1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: bt32 .LBB127_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB127_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_ult(i1 %x) {
+; CHECK-LABEL: brRI_i1_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB128_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB128_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ult i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+
+;ULE
+define i1 @brRR_i1_ule(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a1, a1, 1
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: bf32 .LBB129_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB129_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_ule(i1 %x) {
+; CHECK-LABEL: brRI_i1_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bnez32 a0, .LBB130_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB130_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_ule(i1 %x) {
+; CHECK-LABEL: brR0_i1_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bnez32 a0, .LBB131_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB131_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp ule i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;SGT
+define i1 @brRR_i1_sgt(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sext32 a1, a1, 0, 0
+; CHECK-NEXT: sext32 a0, a0, 0, 0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bf32 .LBB132_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB132_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_sgt(i1 %x) {
+; CHECK-LABEL: brRI_i1_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB133_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB133_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_sgt(i1 %x) {
+; CHECK-LABEL: brR0_i1_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB134_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB134_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sgt i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;SGE
+define i1 @brRR_i1_sge(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sext32 a0, a0, 0, 0
+; CHECK-NEXT: sext32 a1, a1, 0, 0
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bt32 .LBB135_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB135_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_sge(i1 %x) {
+; CHECK-LABEL: brRI_i1_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bnez32 a0, .LBB136_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB136_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_sge(i1 %x) {
+; CHECK-LABEL: brR0_i1_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bnez32 a0, .LBB137_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB137_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sge i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;SLT
+define i1 @brRR_i1_slt(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sext32 a0, a0, 0, 0
+; CHECK-NEXT: sext32 a1, a1, 0, 0
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: bf32 .LBB138_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB138_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_slt(i1 %x) {
+; CHECK-LABEL: brRI_i1_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bnez32 a0, .LBB139_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB139_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_slt(i1 %x) {
+; CHECK-LABEL: brR0_i1_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bnez32 a0, .LBB140_1
+; CHECK-NEXT: # %bb.2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB140_1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp slt i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+;SLE
+define i1 @brRR_i1_sle(i1 %x, i1 %y) {
+; CHECK-LABEL: brRR_i1_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sext32 a1, a1, 0, 0
+; CHECK-NEXT: sext32 a0, a0, 0, 0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: bt32 .LBB141_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB141_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i1 %y, %x
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brRI_i1_sle(i1 %x) {
+; CHECK-LABEL: brRI_i1_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB142_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB142_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i1 %x, 10
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+define i1 @brR0_i1_sle(i1 %x) {
+; CHECK-LABEL: brR0_i1_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB143_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB143_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+; CHECK-UGTXT: icmpu32 a0, a1, a0
+; CHECK-UGTXT: rts16
+entry:
+ %icmp = icmp sle i1 %x, 0
+ br i1 %icmp, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
+
+
+define i1 @brCBit_i1(i1 %c) {
+; CHECK-LABEL: brCBit_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: andi32 a0, a0, 1
+; CHECK-NEXT: bez32 a0, .LBB144_2
+; CHECK-NEXT: # %bb.1: # %label1
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+; CHECK-NEXT: .LBB144_2: # %label2
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ br i1 %c, label %label1, label %label2
+label1:
+ ret i1 1
+label2:
+ ret i1 0
+}
diff --git a/llvm/test/CodeGen/CSKY/cmp-i.ll b/llvm/test/CodeGen/CSKY/cmp-i.ll
new file mode 100644
index 0000000000000..78d115c1d791f
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/cmp-i.ll
@@ -0,0 +1,1533 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
+
+;eq
+define i1 @icmpRR_eq(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_eq(i32 %x) {
+; CHECK-LABEL: icmpRI_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_eq(i32 %x) {
+; CHECK-LABEL: icmpRI_X_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33768
+; CHECK-NEXT: cmpne16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_eq(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a1, a3
+; CHECK-NEXT: xor16 a0, a2
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_eq(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_eq(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_eq(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_eq(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_eq(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_eq(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a0, a1
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_eq(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_eq:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %x, 1
+ ret i1 %icmp
+}
+
+;ne
+define i1 @icmpRR_ne(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_ne(i32 %x) {
+; CHECK-LABEL: icmpRI_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_ne(i32 %x) {
+; CHECK-LABEL: icmpRI_X_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33768
+; CHECK-NEXT: cmpne16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_ne(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a1, a3
+; CHECK-NEXT: xor16 a0, a2
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_ne(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_ne(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_ne(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_ne(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_ne(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_ne(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_ne(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_ne:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %x, 1
+ ret i1 %icmp
+}
+
+
+;ugt
+define i1 @icmpRR_ugt(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_ugt(i32 %x) {
+; CHECK-LABEL: icmpRI_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_ugt(i32 %x) {
+; CHECK-LABEL: icmpRI_X_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33768
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_ugt(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmphs16 a1, a3
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_ugt(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a2, 1
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a2
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: movf32 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_ugt(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_ugt(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: movi16 a1, 1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_ugt(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_ugt(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: movi16 a1, 1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_ugt(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: and16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_ugt(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_ugt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i1 %x, 1
+ ret i1 %icmp
+}
+
+
+;uge
+define i1 @icmpRR_uge(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_uge(i32 %x) {
+; CHECK-LABEL: icmpRI_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_uge(i32 %x) {
+; CHECK-LABEL: icmpRI_X_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33767
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_uge(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: cmphs16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 12)
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a0, (sp, 12)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_uge(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_uge(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_uge(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_uge(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_uge(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_uge(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_uge(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_uge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i1 %x, 1
+ ret i1 %icmp
+}
+
+
+;ult
+define i1 @icmpRR_ult(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_ult(i32 %x) {
+; CHECK-LABEL: icmpRI_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_ult(i32 %x) {
+; CHECK-LABEL: icmpRI_X_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33768
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_ult(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmphs16 a3, a1
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_ult(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_ult(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_ult(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_ult(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_ult(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_ult(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a1, a1, 1
+; CHECK-NEXT: and16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_ult(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_ult:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i1 %x, 1
+ ret i1 %icmp
+}
+
+
+;ule
+define i1 @icmpRR_ule(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_ule(i32 %x) {
+; CHECK-LABEL: icmpRI_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_ule(i32 %x) {
+; CHECK-LABEL: icmpRI_X_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33769
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_ule(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: cmphs16 a1, a3
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 12)
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a0, (sp, 12)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_ule(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: cmphsi16 a0, 2
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_ule(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_ule(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 2
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_ule(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_ule(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 2
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_ule(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a1, a1, 1
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_ule(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_ule:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i1 %x, 1
+ ret i1 %icmp
+}
+
+;sgt
+define i1 @icmpRR_sgt(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_sgt(i32 %x) {
+; CHECK-LABEL: icmpRI_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 10
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_sgt(i32 %x) {
+; CHECK-LABEL: icmpRI_X_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33768
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_sgt(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmplt16 a1, a3
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_sgt(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a2, a1
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 8)
+; CHECK-NEXT: movi16 a2, 1
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a2
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: ld16.w a0, (sp, 8)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movf32 a0, a2
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_sgt(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_sgt(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi16 a1, 1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_sgt(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_sgt(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movi16 a1, 1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_sgt(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a1, a1, 1
+; CHECK-NEXT: and16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_sgt(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_sgt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i1 %x, 1
+ ret i1 %icmp
+}
+
+;sge
+define i1 @icmpRR_sge(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_sge(i32 %x) {
+; CHECK-LABEL: icmpRI_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a1, 9
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_sge(i32 %x) {
+; CHECK-LABEL: icmpRI_X_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33767
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_sge(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: cmplt16 a3, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_sge(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a2, a1
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 12)
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a0, (sp, 12)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_sge(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_sge(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_sge(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_sge(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_sge(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a1, a1, 1
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_sge(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_sge:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i1 %x, 1
+ ret i1 %icmp
+}
+
+;slt
+define i1 @icmpRR_slt(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_slt(i32 %x) {
+; CHECK-LABEL: icmpRI_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplti16 a0, 10
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_slt(i32 %x) {
+; CHECK-LABEL: icmpRI_X_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33768
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_slt(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmplt16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_slt(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a1, a2
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_slt(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_slt(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_slt(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_slt(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_slt(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: and16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_slt(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_slt:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i1 %x, 1
+ ret i1 %icmp
+}
+
+
+;sle
+define i1 @icmpRR_sle(i32 %x, i32 %y) {
+; CHECK-LABEL: icmpRR_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i32 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_sle(i32 %x) {
+; CHECK-LABEL: icmpRI_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplti16 a0, 11
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i32 %x, 10
+ ret i1 %icmp
+}
+
+define i1 @icmpRI_X_sle(i32 %x) {
+; CHECK-LABEL: icmpRI_X_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a1, 62
+; CHECK-NEXT: ori32 a1, a1, 33769
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i32 %x, 4097000
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_sle(i64 %x, i64 %y) {
+; CHECK-LABEL: ICMP_LONG_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: cmplt16 a1, a3
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i64 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_LONG_I_sle(i64 %x) {
+; CHECK-LABEL: ICMP_LONG_I_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: movi16 a2, 0
+; CHECK-NEXT: cmplt16 a1, a2
+; CHECK-NEXT: mvc32 a2
+; CHECK-NEXT: st16.w a2, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphsi16 a0, 2
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i64 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_sle(i16 %x, i16 %y) {
+; CHECK-LABEL: ICMP_SHORT_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i16 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_SHORT_I_sle(i16 %x) {
+; CHECK-LABEL: ICMP_SHORT_I_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i16 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_sle(i8 %x, i8 %y) {
+; CHECK-LABEL: ICMP_CHAR_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i8 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_CHAR_I_sle(i8 %x) {
+; CHECK-LABEL: ICMP_CHAR_I_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i8 %x, 1
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_sle(i1 %x, i1 %y) {
+; CHECK-LABEL: ICMP_BIT_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xori32 a0, a0, 1
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i1 %y, %x
+ ret i1 %icmp
+}
+
+define i1 @ICMP_BIT_I_sle(i1 %x) {
+; CHECK-LABEL: ICMP_BIT_I_sle:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i1 %x, 1
+ ret i1 %icmp
+}
diff --git a/llvm/test/CodeGen/CSKY/select.ll b/llvm/test/CodeGen/CSKY/select.ll
new file mode 100644
index 0000000000000..416bb158f0f2d
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/select.ll
@@ -0,0 +1,3353 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
+
+define i32 @selectRR_eq_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_eq_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_eq_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_eq_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_eq_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_eq_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2033
+; CHECK-NEXT: cmpne16 a0, a3
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_eq_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_eq_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_eq_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_eq_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a1, a3
+; CHECK-NEXT: xor16 a0, a2
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: addu16 a0, sp
+; CHECK-NEXT: mov16 a1, a0
+; CHECK-NEXT: addi16 a0, sp, 8
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: ld16.w a0, (a1, 0)
+; CHECK-NEXT: ld16.w a1, (a1, 4)
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_eq_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_eq_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 4)
+; CHECK-NEXT: ld32.w t1, (sp, 0)
+; CHECK-NEXT: xori32 a0, a0, 10
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: movf32 a2, t1
+; CHECK-NEXT: movf32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_eq_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_eq_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2033
+; CHECK-NEXT: xor16 a0, l0
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: movf32 a2, t1
+; CHECK-NEXT: movf32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_eq_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_eq_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_eq_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_eq_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_eq_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_eq_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_eq_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_eq_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei32 a0, 2033
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_eq_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_eq_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_eq_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_eq_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_eq_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_eq_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_eq_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_eq_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei32 a0, 241
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_eq_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_eq_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_eq_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_eq_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a0, a1
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: mov16 a0, a3
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_eq_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_eq_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_eq_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_eq_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp eq i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_eq_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_eq_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+
+define i32 @selectRR_ne_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_ne_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_ne_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_ne_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_ne_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_ne_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2033
+; CHECK-NEXT: cmpne16 a0, a3
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_ne_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_ne_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_ne_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_ne_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a1, a3
+; CHECK-NEXT: xor16 a0, a2
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: movi16 a0, 0
+; CHECK-NEXT: addu16 a0, sp
+; CHECK-NEXT: mov16 a1, a0
+; CHECK-NEXT: addi16 a0, sp, 8
+; CHECK-NEXT: movt32 a1, a0
+; CHECK-NEXT: ld16.w a0, (a1, 0)
+; CHECK-NEXT: ld16.w a1, (a1, 4)
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_ne_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_ne_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 4)
+; CHECK-NEXT: ld32.w t1, (sp, 0)
+; CHECK-NEXT: xori32 a0, a0, 10
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_ne_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_ne_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2033
+; CHECK-NEXT: xor16 a0, l0
+; CHECK-NEXT: or16 a0, a1
+; CHECK-NEXT: cmpnei16 a0, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_ne_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_ne_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_ne_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_ne_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_ne_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_ne_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_ne_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_ne_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmpnei32 a0, 2033
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_ne_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_ne_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_ne_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_ne_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmpne16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_ne_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_ne_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei16 a0, 10
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_ne_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_ne_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmpnei32 a0, 241
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_ne_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_ne_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_ne_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_ne_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xor16 a0, a1
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_ne_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_ne_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_ne_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_ne_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ne i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_ne_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_ne_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+
+define i32 @selectRR_ugt_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_ugt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_ugt_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_ugt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a3, 10
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_ugt_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_ugt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2033
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_ugt_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_ugt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_ugt_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_ugt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmphs16 a1, a3
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: addi16 a2, sp, 8
+; CHECK-NEXT: addi16 a0, sp, 16
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a0
+; CHECK-NEXT: ld16.w a0, (a2, 0)
+; CHECK-NEXT: ld16.w a1, (a2, 4)
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_ugt_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_ugt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movi16 l0, 10
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_ugt_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_ugt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2033
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_ugt_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_ugt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_ugt_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_ugt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_ugt_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_ugt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: movi16 a3, 10
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_ugt_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_ugt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: movi32 a3, 2033
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_ugt_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_ugt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_ugt_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_ugt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_ugt_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_ugt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: movi16 a3, 10
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_ugt_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_ugt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: movi16 a3, 241
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_ugt_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_ugt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_ugt_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_ugt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_ugt_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_ugt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_ugt_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_ugt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ugt i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_ugt_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_ugt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+
+define i32 @selectRR_uge_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_uge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_uge_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_uge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a3, 9
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_uge_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_uge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2032
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_uge_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_uge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_uge_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_uge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: cmphs16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 12)
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a1, (sp, 12)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: addi16 a2, sp, 16
+; CHECK-NEXT: addi16 a0, sp, 24
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a0
+; CHECK-NEXT: ld16.w a0, (a2, 0)
+; CHECK-NEXT: ld16.w a1, (a2, 4)
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_uge_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_uge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movi16 l0, 9
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_uge_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_uge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2032
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_uge_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_uge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_uge_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_uge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_uge_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_uge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: movi16 a3, 9
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_uge_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_uge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: movi32 a3, 2032
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_uge_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_uge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_uge_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_uge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_uge_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_uge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: movi16 a3, 9
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_uge_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_uge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: movi16 a3, 240
+; CHECK-NEXT: cmphs16 a3, a0
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_uge_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_uge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_uge_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_uge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mov16 a0, a3
+; CHECK-NEXT: movt32 a0, a2
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a0, a3
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_uge_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_uge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_uge_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_uge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp uge i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_uge_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_uge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+
+define i32 @selectRR_ult_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_ult_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_ult_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_ult_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_ult_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_ult_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2033
+; CHECK-NEXT: cmphs16 a0, a3
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_ult_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_ult_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_ult_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_ult_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmphs16 a3, a1
+; CHECK-NEXT: mvcv16 a1
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: addi16 a2, sp, 8
+; CHECK-NEXT: addi16 a0, sp, 16
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a0
+; CHECK-NEXT: ld16.w a0, (a2, 0)
+; CHECK-NEXT: ld16.w a1, (a2, 4)
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_ult_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_ult_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: ld32.w t0, (sp, 12)
+; CHECK-NEXT: ld32.w t1, (sp, 8)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: st16.w a2, (sp, 0)
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: ld16.w a2, (sp, 0)
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_ult_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_ult_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2033
+; CHECK-NEXT: cmphs16 a0, l0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_ult_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_ult_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_ult_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_ult_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_ult_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_ult_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_ult_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_ult_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphsi32 a0, 2033
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_ult_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_ult_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_ult_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_ult_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: cmphs16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_ult_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_ult_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_ult_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_ult_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphsi32 a0, 241
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_ult_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_ult_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_ult_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_ult_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_ult_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_ult_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_ult_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_ult_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ult i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_ult_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_ult_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i32 @selectRR_ule_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_ule_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_ule_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_ule_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_ule_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_ule_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2034
+; CHECK-NEXT: cmphs16 a0, a3
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_ule_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_ule_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_ule_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_ule_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: cmphs16 a1, a3
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 12)
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: ld16.w a0, (sp, 4)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: ld16.w a1, (sp, 12)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: addi16 a2, sp, 16
+; CHECK-NEXT: addi16 a0, sp, 24
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a0
+; CHECK-NEXT: ld16.w a0, (a2, 0)
+; CHECK-NEXT: ld16.w a1, (a2, 4)
+; CHECK-NEXT: addi16 sp, sp, 16
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_ule_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_ule_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 8
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: ld32.w t0, (sp, 12)
+; CHECK-NEXT: ld32.w t1, (sp, 8)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: st16.w a2, (sp, 0)
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: ld16.w a2, (sp, 4)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: ld16.w a2, (sp, 0)
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 8
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_ule_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_ule_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: ld32.w t0, (sp, 8)
+; CHECK-NEXT: ld32.w t1, (sp, 4)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2034
+; CHECK-NEXT: cmphs16 a0, l0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: movi16 a1, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_ule_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_ule_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_ule_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_ule_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a1, a1
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_ule_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_ule_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_ule_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_ule_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zexth16 a0, a0
+; CHECK-NEXT: cmphsi32 a0, 2034
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_ule_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_ule_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_ule_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_ule_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a1, a1
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphs16 a0, a1
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_ule_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_ule_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_ule_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_ule_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: zextb16 a0, a0
+; CHECK-NEXT: cmphsi32 a0, 242
+; CHECK-NEXT: movf32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_ule_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_ule_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_ule_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_ule_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_ule_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_ule_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_ule_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_ule_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp ule i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_ule_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_ule_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+
+define i32 @selectRR_sgt_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_sgt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_sgt_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_sgt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a3, 10
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_sgt_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_sgt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2033
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_sgt_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_sgt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_sgt_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_sgt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmplt16 a1, a3
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: addi16 a2, sp, 12
+; CHECK-NEXT: addi16 a0, sp, 20
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a0
+; CHECK-NEXT: ld16.w a0, (a2, 0)
+; CHECK-NEXT: ld16.w a1, (a2, 4)
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_sgt_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_sgt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 l0, a1
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 8)
+; CHECK-NEXT: movi16 l0, 10
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 4)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_sgt_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_sgt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 l0, a1
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 8)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2033
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 4)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_sgt_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_sgt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_sgt_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_sgt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_sgt_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_sgt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi16 a3, 10
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_sgt_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_sgt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi32 a3, 2033
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_sgt_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_sgt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_sgt_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_sgt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_sgt_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_sgt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movi16 a3, 10
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_sgt_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_sgt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movih32 a3, 65535
+; CHECK-NEXT: ori32 a3, a3, 65521
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_sgt_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_sgt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_sgt_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_sgt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_sgt_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_sgt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_sgt_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_sgt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sgt i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_sgt_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_sgt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+
+define i32 @selectRR_sge_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_sge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_sge_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_sge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movi16 a3, 9
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_sge_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_sge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2032
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_sge_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_sge_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_sge_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_sge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: cmplt16 a3, a1
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 a1, sp, 12
+; CHECK-NEXT: addi16 a2, sp, 20
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: ld16.w a0, (a1, 0)
+; CHECK-NEXT: ld16.w a1, (a1, 4)
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_sge_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_sge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 l0, a1
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 8)
+; CHECK-NEXT: movi16 l0, 9
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 4)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_sge_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_sge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 l0, a1
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 8)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2032
+; CHECK-NEXT: cmphs16 l0, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 4)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_sge_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_sge_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_sge_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_sge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_sge_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_sge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi16 a3, 9
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_sge_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_sge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: movi32 a3, 2032
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_sge_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_sge_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_sge_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_sge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_sge_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_sge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movi16 a3, 9
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_sge_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_sge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movih32 a3, 65535
+; CHECK-NEXT: ori32 a3, a3, 65520
+; CHECK-NEXT: cmplt16 a3, a0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_sge_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_sge_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_sge_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_sge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_sge_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_sge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a2, a1
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_sge_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_sge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sge i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_sge_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_sge_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+
+define i32 @selectRR_slt_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_slt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_slt_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_slt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplti16 a0, 10
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_slt_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_slt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2033
+; CHECK-NEXT: cmplt16 a0, a3
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_slt_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_slt_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_slt_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_slt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmplt16 a3, a1
+; CHECK-NEXT: mvc32 t0
+; CHECK-NEXT: st32.w t0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphs16 a2, a0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: addi16 a2, sp, 12
+; CHECK-NEXT: addi16 a0, sp, 20
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a0
+; CHECK-NEXT: ld16.w a0, (a2, 0)
+; CHECK-NEXT: ld16.w a1, (a2, 4)
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_slt_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_slt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 a1, l0
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphsi16 a0, 10
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 8)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_slt_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_slt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 a1, l0
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 8)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2033
+; CHECK-NEXT: cmphs16 a0, l0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 4)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_slt_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_slt_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_slt_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_slt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_slt_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_slt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 10
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_slt_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_slt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti32 a0, 2033
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_slt_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_slt_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_slt_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_slt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: cmplt16 a1, a0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_slt_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_slt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 10
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_slt_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_slt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movih32 a3, 65535
+; CHECK-NEXT: ori32 a3, a3, 65521
+; CHECK-NEXT: cmplt16 a0, a3
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_slt_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_slt_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_slt_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_slt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a3, a2
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_slt_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_slt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_slt_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_slt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp slt i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_slt_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_slt_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i32 @selectRR_sle_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRR_sle_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i32 %y, %x
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRI_sle_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRI_sle_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cmplti16 a0, 11
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i32 %x, 10
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectRX_sle_i32(i32 %x, i32 %n, i32 %m) {
+; CHECK-LABEL: selectRX_sle_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movih32 a3, 729
+; CHECK-NEXT: ori32 a3, a3, 2034
+; CHECK-NEXT: cmplt16 a0, a3
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i32 %x, 47777777
+ %ret = select i1 %icmp, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i32 @selectC_sle_i32(i1 %c, i32 %n, i32 %m) {
+; CHECK-LABEL: selectC_sle_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i32 %m, i32 %n
+ ret i32 %ret
+}
+
+define i64 @selectRR_sle_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRR_sle_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: .cfi_def_cfa_offset 0
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 12
+; CHECK-NEXT: cmphs16 a0, a2
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 4)
+; CHECK-NEXT: cmpne16 a3, a1
+; CHECK-NEXT: mvc32 a0
+; CHECK-NEXT: st16.w a0, (sp, 8)
+; CHECK-NEXT: cmplt16 a1, a3
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w a2, (sp, 8)
+; CHECK-NEXT: btsti32 a2, 0
+; CHECK-NEXT: movf32 a0, a1
+; CHECK-NEXT: addi16 a1, sp, 12
+; CHECK-NEXT: addi16 a2, sp, 20
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: ld16.w a0, (a1, 0)
+; CHECK-NEXT: ld16.w a1, (a1, 4)
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i64 %y, %x
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRI_sle_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRI_sle_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 a1, l0
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 4)
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 8)
+; CHECK-NEXT: cmphsi16 a0, 11
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: ld16.w a1, (sp, 4)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 8)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i64 %x, 10
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectRX_sle_i64(i64 %x, i64 %n, i64 %m) {
+; CHECK-LABEL: selectRX_sle_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subi16 sp, sp, 4
+; CHECK-NEXT: .cfi_def_cfa_offset 4
+; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset l0, -4
+; CHECK-NEXT: subi16 sp, sp, 12
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: ld32.w t0, (sp, 20)
+; CHECK-NEXT: ld32.w t1, (sp, 16)
+; CHECK-NEXT: movi16 l0, 0
+; CHECK-NEXT: cmplt16 a1, l0
+; CHECK-NEXT: mvc32 l0
+; CHECK-NEXT: st16.w l0, (sp, 8)
+; CHECK-NEXT: movih32 l0, 729
+; CHECK-NEXT: ori32 l0, l0, 2034
+; CHECK-NEXT: cmphs16 a0, l0
+; CHECK-NEXT: mvcv16 a0
+; CHECK-NEXT: cmpnei16 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: st16.w a1, (sp, 4)
+; CHECK-NEXT: ld16.w a1, (sp, 8)
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: mvc32 a1
+; CHECK-NEXT: ld16.w l0, (sp, 4)
+; CHECK-NEXT: btsti32 l0, 0
+; CHECK-NEXT: movf32 a1, a0
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a2, t1
+; CHECK-NEXT: movt32 a3, t0
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: mov16 a1, a3
+; CHECK-NEXT: addi16 sp, sp, 12
+; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload
+; CHECK-NEXT: addi16 sp, sp, 4
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i64 %x, 47777777
+ %ret = select i1 %icmp, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+define i64 @selectC_sle_i64(i1 %c, i64 %n, i64 %m) {
+; CHECK-LABEL: selectC_sle_i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld32.w t0, (sp, 0)
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a3
+; CHECK-NEXT: movt32 a2, t0
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: mov16 a1, a2
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i64 %m, i64 %n
+ ret i64 %ret
+}
+
+
+define i16 @selectRR_sle_i16(i16 %x, i16 %y, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRR_sle_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a1, a1
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i16 %y, %x
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRI_sle_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRI_sle_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 11
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i16 %x, 10
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectRX_sle_i16(i16 %x, i16 %n, i16 %m) {
+; CHECK-LABEL: selectRX_sle_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sexth16 a0, a0
+; CHECK-NEXT: cmplti32 a0, 2034
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i16 %x, 47777777
+ %ret = select i1 %icmp, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+define i16 @selectC_sle_i16(i1 %c, i16 %n, i16 %m) {
+; CHECK-LABEL: selectC_sle_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i16 %m, i16 %n
+ ret i16 %ret
+}
+
+
+define i8 @selectRR_sle_i8(i8 %x, i8 %y, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRR_sle_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a1, a1
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplt16 a0, a1
+; CHECK-NEXT: movf32 a2, a3
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i8 %y, %x
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRI_sle_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRI_sle_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: cmplti16 a0, 11
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i8 %x, 10
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectRX_sle_i8(i8 %x, i8 %n, i8 %m) {
+; CHECK-LABEL: selectRX_sle_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sextb16 a0, a0
+; CHECK-NEXT: movih32 a3, 65535
+; CHECK-NEXT: ori32 a3, a3, 65522
+; CHECK-NEXT: cmplt16 a0, a3
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i8 %x, 47777777
+ %ret = select i1 %icmp, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+define i8 @selectC_sle_i8(i1 %c, i8 %n, i8 %m) {
+; CHECK-LABEL: selectC_sle_i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i8 %m, i8 %n
+ ret i8 %ret
+}
+
+
+define i1 @selectRR_sle_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRR_sle_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: mov16 a0, a3
+; CHECK-NEXT: movt32 a0, a2
+; CHECK-NEXT: btsti32 a1, 0
+; CHECK-NEXT: movt32 a0, a3
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i1 %y, %x
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRI_sle_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRI_sle_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mov16 a0, a2
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i1 %x, 10
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectRX_sle_i1(i1 %x, i1 %n, i1 %m) {
+; CHECK-LABEL: selectRX_sle_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %icmp = icmp sle i1 %x, 47777777
+ %ret = select i1 %icmp, i1 %m, i1 %n
+ ret i1 %ret
+}
+
+define i1 @selectC_sle_i1(i1 %c, i1 %n, i1 %m) {
+; CHECK-LABEL: selectC_sle_i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: movt32 a1, a2
+; CHECK-NEXT: mov16 a0, a1
+; CHECK-NEXT: rts16
+entry:
+ %ret = select i1 %c, i1 %m, i1 %n
+ ret i1 %ret
+}
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