[PATCH] D116584: [RISCV] Block vmsltu.vx/vmsgeu.vi with 0 immediate in Isel

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:817
       break;
+    case Intrinsic::riscv_vmsltu: {
+      SDValue Src1 = Node->getOperand(1);
----------------
craig.topper wrote:
> Chenbing.Zheng wrote:
> > craig.topper wrote:
> > > This could be done by using a new version of simm5_plus1 that excludes 0 in VPatCompare_VI for the vmsltu case.
> > New simm5_plus1 excludes 0, and  I Keep pattern  "defm : VPatCompareUnsignedZero<"int_riscv_vmsltu", "PseudoVMSNE">" to match vmsltu 0，and del this two case.  Understanding right ?
> Remove the VPatCOmpareUnisignedZero. The vmsltu.vx will then be able to match. The 0 will select to X0.
I try it, but  vmsleu.vi -1 still generate. 
VPattern of vmsltu.vx is different from vmsltu.vi , it cause vmsltu.vx canot be match ?
So I keep these two cases, and delate VPatCompareUnsignedZero in my newest patch.


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  https://reviews.llvm.org/D116584/new/

https://reviews.llvm.org/D116584