[PATCH] D116602: [SVE][CodeGen] Add support for scalable vectors in AArch64TargetLowering::ReconstructShuffle

[David Sherwood via Phabricator via llvm-commits]

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Previously the code in AArch64TargetLowering::ReconstructShuffle assumed
the input vectors were always fixed-width, however this is not always
the case since you can extract elements from scalable vectors and insert
into fixed-width ones. We were hitting crashes here for two different
cases:

1. When lowering a fixed-length vector extract from a scalable vector

with i1 element types. This happens due to the fact the i1 elements
get promoted to larger integer types for fixed-width vectors and leads
to sequences of INSERT_VECTOR_ELT and EXTRACT_VECTOR_ELT nodes. In this
case AArch64TargetLowering::ReconstructShuffle will still fail to make
a transformation, but at least it no longer crashes.

2. When lowering a sequence of extractelement/insertelement operations

on mixed fixed-width/scalable vectors. There are cases when the
transformation succeeds and produces far better code than if we just
immediately bail out for scalable vectors.

Tests for both instances described above have been added here:

  (1) CodeGen/AArch64/sve-extract-fixed-vector.ll
  (2) CodeGen/AArch64/sve-fixed-length-reshuffle.ll

I have tried to highlight in sve-fixed-length-reshuffle.ll those tests
that exercise the AArch64TargetLowering::ReconstructShuffle code path
when the transformation succeeds or fails. For completeness I have
also added similar tests for other cases that do not exercise the
AArch64TargetLowering::ReconstructShuffle code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116602

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-reshuffle.ll

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