[llvm] 95b74d4 - [JITLink] Improve extractBits function

[via llvm-commits]

Author: luxufan
Date: 2022-01-04T20:05:50+08:00
New Revision: 95b74d4db0686a8d55fdae1af4e985ea52b2c572

URL: https://github.com/llvm/llvm-project/commit/95b74d4db0686a8d55fdae1af4e985ea52b2c572
DIFF: https://github.com/llvm/llvm-project/commit/95b74d4db0686a8d55fdae1af4e985ea52b2c572.diff

LOG: [JITLink] Improve extractBits function

Address the advice proposed at patch D105429 . Use [Low, Low+size) to represent bits.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D107250

Added: 
    

Modified: 
    llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

Removed: 
    


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diff  --git a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
index b057788ce3efc..26ec79ea50cf9 100644
--- a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
+++ b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
@@ -157,8 +157,8 @@ static Expected<const Edge &> getRISCVPCRelHi20(const Edge &E) {
       "No HI20 PCREL relocation type be found for LO12 PCREL relocation type");
 }
 
-static uint32_t extractBits(uint64_t Num, unsigned High, unsigned Low) {
-  return (Num & ((1ULL << (High + 1)) - 1)) >> Low;
+static uint32_t extractBits(uint32_t Num, unsigned Low, unsigned Size) {
+  return (Num & (((1ULL << (Size + 1)) - 1) << Low)) >> Low;
 }
 
 class ELFJITLinker_riscv : public JITLinker<ELFJITLinker_riscv> {
@@ -238,8 +238,8 @@ class ELFJITLinker_riscv : public JITLinker<ELFJITLinker_riscv> {
       int64_t Value = RelHI20->getTarget().getAddress() +
                       RelHI20->getAddend() - E.getTarget().getAddress();
       int64_t Lo = Value & 0xFFF;
-      uint32_t Imm31_25 = extractBits(Lo, 11, 5) << 25;
-      uint32_t Imm11_7 = extractBits(Lo, 4, 0) << 7;
+      uint32_t Imm31_25 = extractBits(Lo, 5, 7) << 25;
+      uint32_t Imm11_7 = extractBits(Lo, 0, 5) << 7;
       uint32_t RawInstr = *(little32_t *)FixupPtr;
 
       *(little32_t *)FixupPtr = (RawInstr & 0x1FFF07F) | Imm31_25 | Imm11_7;