[PATCH] D116584: [RISCV] Block vmsleu.vx/vmsgeu.vi with 0 immediate in Isel

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng created this revision.
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For vmsleu.vi we block the 0 immediate from matching in isel and let vmsleu.vx with X0 match.
For vmsgeu.vi there is no vmsgeu.vx instruction, but we know this is always true,
so we instead with vmset.m(for unmasked) and vmand.mm(for masked).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116584

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

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