[llvm] 9fb4e79 - Revert "[AVR] Optimize int8 arithmetic right shift 6 bits"

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2022-01-04T04:14:15Z
New Revision: 9fb4e79d06aa690c611c0ef601c134f57788590a

URL: https://github.com/llvm/llvm-project/commit/9fb4e79d06aa690c611c0ef601c134f57788590a
DIFF: https://github.com/llvm/llvm-project/commit/9fb4e79d06aa690c611c0ef601c134f57788590a.diff

LOG: Revert "[AVR] Optimize int8 arithmetic right shift 6 bits"

This reverts commit 5723261370b45fa4d0d295845c6ef9e223f2ff4a.

There are failures as reported in

https://lab.llvm.org/buildbot#builders/16/builds/21638
https://lab.llvm.org/buildbot#builders/104/builds/5394

Added: 
    

Modified: 
    llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
    llvm/lib/Target/AVR/AVRISelLowering.cpp
    llvm/test/CodeGen/AVR/shift.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
index 16c94981947e6..cb85d73772c55 100644
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -92,7 +92,6 @@ class AVRExpandPseudo : public MachineFunctionPass {
   /// Specific shift implementation.
   bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
   bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
-  bool expandASRB6Rd(Block &MBB, BlockIt MBBI);
   bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
   bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
   bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
@@ -1922,49 +1921,6 @@ bool AVRExpandPseudo::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
   }
 }
 
-bool AVRExpandPseudo::expandASRB6Rd(Block &MBB, BlockIt MBBI) {
-  MachineInstr &MI = *MBBI;
-  Register DstReg = MI.getOperand(0).getReg();
-  bool DstIsDead = MI.getOperand(0).isDead();
-  bool DstIsKill = MI.getOperand(1).isKill();
-  bool ImpIsDead = MI.getOperand(3).isDead();
-
-  // bst r24, 6
-  // lsl r24
-  // sbc r24, r24
-  // bld r24, 0
-
-  buildMI(MBB, MBBI, AVR::BST)
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addImm(6)
-      ->getOperand(2)
-      .setIsUndef(true);
-
-  buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rd
-      .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
-
-  auto MISBC =
-      buildMI(MBB, MBBI, AVR::SBCRdRr)
-          .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstReg, getKillRegState(DstIsKill))
-          .addReg(DstReg, getKillRegState(DstIsKill));
-
-  buildMI(MBB, MBBI, AVR::BLD)
-      .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addImm(0)
-      ->getOperand(3)
-      .setIsKill();
-
-  if (ImpIsDead)
-    MISBC->getOperand(3).setIsDead();
-
-  MI.eraseFromParent();
-  return true;
-}
-
 bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   Register DstReg = MI.getOperand(0).getReg();
@@ -2001,8 +1957,6 @@ bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
   MachineInstr &MI = *MBBI;
   unsigned Imm = MI.getOperand(2).getImm();
   switch (Imm) {
-  case 6:
-    return expandASRB6Rd(MBB, MBBI);
   case 7:
     return expandASRB7Rd(MBB, MBBI);
   default:

diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index f3e74e8436956..39fba74a1ec78 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -359,11 +359,6 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
       Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim,
                            DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
-    } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
-      // Optimize ASR when ShiftAmount == 6.
-      Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
-                           DAG.getConstant(6, dl, VT));
-      ShiftAmount = 0;
     } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
       // Optimize ASR when ShiftAmount == 7.
       Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,

diff  --git a/llvm/test/CodeGen/AVR/shift.ll b/llvm/test/CodeGen/AVR/shift.ll
index d36655a2cb753..24bc369cf6143 100644
--- a/llvm/test/CodeGen/AVR/shift.ll
+++ b/llvm/test/CodeGen/AVR/shift.ll
@@ -171,16 +171,6 @@ define i8 @lsr_i8_7(i8 %a) {
   ret i8 %result
 }
 
-define i8 @asr_i8_6(i8 %a) {
-; CHECK-LABEL: asr_i8_6
-; CHECK:      bst r24, 6
-; CHECK-NEXT: lsl r24
-; CHECK-NEXT: sbc r24, r24
-; CHECK-NEXT: bld r24, 0
-  %result = ashr i8 %a, 6
-  ret i8 %result
-}
-
 define i8 @asr_i8_7(i8 %a) {
 ; CHECK-LABEL: asr_i8_7
 ; CHECK:      lsl r24