[PATCH] D116277: [RISCV] Use vmv.s.x to build one element splat vector.
Zakk Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 3 09:32:53 PST 2022
khchen added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll:1599
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
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Spec said `If SEW > XLEN, the value is sign-extended to SEW bits.`
Does it mean we could also use vmv.s.x here?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D116277/new/
https://reviews.llvm.org/D116277
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