[llvm] 4602f41 - [RISCV] Prune unnecessary vector pseudo instructions. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 1 20:45:41 PST 2022
Author: Craig Topper
Date: 2022-01-01T19:53:53-08:00
New Revision: 4602f4169a21e75b82261ba1599046b157d1d021
URL: https://github.com/llvm/llvm-project/commit/4602f4169a21e75b82261ba1599046b157d1d021
DIFF: https://github.com/llvm/llvm-project/commit/4602f4169a21e75b82261ba1599046b157d1d021.diff
LOG: [RISCV] Prune unnecessary vector pseudo instructions. NFC
For .vf instructions, we don't need MF8 pseudos for f16. We don't
need MF8 or MF4 pseudos for f32. Or MF8, MF4, MF2 for f64.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D116437
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 15a75ba411c04..d39e0805a79c2 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -473,21 +473,15 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
case RISCV::PseudoVFMV_S_F16_M8:
case RISCV::PseudoVFMV_S_F16_MF2:
case RISCV::PseudoVFMV_S_F16_MF4:
- case RISCV::PseudoVFMV_S_F16_MF8:
case RISCV::PseudoVFMV_S_F32_M1:
case RISCV::PseudoVFMV_S_F32_M2:
case RISCV::PseudoVFMV_S_F32_M4:
case RISCV::PseudoVFMV_S_F32_M8:
case RISCV::PseudoVFMV_S_F32_MF2:
- case RISCV::PseudoVFMV_S_F32_MF4:
- case RISCV::PseudoVFMV_S_F32_MF8:
case RISCV::PseudoVFMV_S_F64_M1:
case RISCV::PseudoVFMV_S_F64_M2:
case RISCV::PseudoVFMV_S_F64_M4:
case RISCV::PseudoVFMV_S_F64_M8:
- case RISCV::PseudoVFMV_S_F64_MF2:
- case RISCV::PseudoVFMV_S_F64_MF4:
- case RISCV::PseudoVFMV_S_F64_MF8:
return true;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index dee1ce635c735..9dc2bcb363227 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1400,19 +1400,28 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL) \
RISCV::PseudoV##OP##_##TYPE##_##LMUL
-#define CASE_VFMA_OPCODE_LMULS(OP, TYPE) \
- CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8): \
- case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4): \
- case CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2): \
- case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1): \
+#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE) \
+ CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4): \
case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8)
+#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE) \
+ CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2): \
+ case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE)
+
+#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE) \
+ CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4): \
+ case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE)
+
+#define CASE_VFMA_OPCODE_LMULS(OP, TYPE) \
+ CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF8): \
+ case CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE)
+
#define CASE_VFMA_SPLATS(OP) \
- CASE_VFMA_OPCODE_LMULS(OP, VF16): \
- case CASE_VFMA_OPCODE_LMULS(OP, VF32): \
- case CASE_VFMA_OPCODE_LMULS(OP, VF64)
+ CASE_VFMA_OPCODE_LMULS_MF4(OP, VF16): \
+ case CASE_VFMA_OPCODE_LMULS_MF2(OP, VF32): \
+ case CASE_VFMA_OPCODE_LMULS_M1(OP, VF64)
// clang-format on
bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
@@ -1534,19 +1543,28 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
break;
-#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \
- CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
- CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
- CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
+#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
+#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE) \
+ CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
+ CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE)
+
+#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE) \
+ CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
+ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE)
+
+#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \
+ CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
+ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE)
+
#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \
- CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF16) \
- CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF32) \
- CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, VF64)
+ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VF16) \
+ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VF32) \
+ CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VF64)
MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
bool NewMI,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index dca3f53188125..40ab0bb204020 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -85,27 +85,28 @@ defvar MxListVF4 = [V_MF2, V_M1, V_M2, V_M4, V_M8];
// Use for zext/sext.vf8
defvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8];
-class FPR_Info<RegisterClass regclass, string fx> {
+class MxSet<int eew> {
+ list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
+ !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
+}
+
+class FPR_Info<RegisterClass regclass, string fx, list<LMULInfo> mxlist> {
RegisterClass fprclass = regclass;
string FX = fx;
+ list<LMULInfo> MxList = mxlist;
}
-def SCALAR_F16 : FPR_Info<FPR16, "F16">;
-def SCALAR_F32 : FPR_Info<FPR32, "F32">;
-def SCALAR_F64 : FPR_Info<FPR64, "F64">;
+def SCALAR_F16 : FPR_Info<FPR16, "F16", MxSet<16>.m>;
+def SCALAR_F32 : FPR_Info<FPR32, "F32", MxSet<32>.m>;
+def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m>;
defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
// Used for widening instructions. It excludes F64.
defvar FPListW = [SCALAR_F16, SCALAR_F32];
-class MxSet<int eew> {
- list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
- !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
- !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
- !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
-}
-
class NFSet<LMULInfo m> {
list<int> L = !cond(!eq(m.value, V_M8.value): [],
!eq(m.value, V_M4.value): [2],
@@ -1619,15 +1620,15 @@ multiclass VPseudoVSLD1_VX<string Constraint = ""> {
}
multiclass VPseudoBinaryV_VF<string Constraint = ""> {
- foreach m = MxList in
- foreach f = FPList in
+ foreach f = FPList in
+ foreach m = f.MxList in
defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass,
f.fprclass, m, Constraint>;
}
multiclass VPseudoVSLD1_VF<string Constraint = ""> {
- foreach m = MxList in
- foreach f = FPList in
+ foreach f = FPList in
+ foreach m = f.MxList in
defm "_V" # f.FX :
VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
Sched<[WriteVFSlide1F, ReadVFSlideV, ReadVFSlideF, ReadVMask]>;
@@ -1666,8 +1667,8 @@ multiclass VPseudoBinaryW_VX {
}
multiclass VPseudoBinaryW_VF {
- foreach m = MxListW in
- foreach f = FPListW in
+ foreach f = FPListW in
+ foreach m = f.MxList in
defm "_V" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass,
f.fprclass, m,
"@earlyclobber $rd">;
@@ -1688,8 +1689,8 @@ multiclass VPseudoBinaryW_WX {
}
multiclass VPseudoBinaryW_WF {
- foreach m = MxListW in
- foreach f = FPListW in
+ foreach f = FPListW in
+ foreach m = f.MxList in
defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass,
f.fprclass, m>;
}
@@ -1741,8 +1742,8 @@ multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
}
multiclass VPseudoVMRG_FM {
- foreach m = MxList in
- foreach f = FPList in
+ foreach f = FPList in
+ foreach m = f.MxList in
def "_V" # f.FX # "M_" # m.MX :
VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
@@ -1773,8 +1774,8 @@ multiclass VPseudoUnaryVMV_V_X_I {
}
multiclass VPseudoVMV_F {
- foreach m = MxList in {
- foreach f = FPList in {
+ foreach f = FPList in {
+ foreach m = f.MxList in {
let VLMul = m.value in {
def "_" # f.FX # "_" # m.MX :
VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>,
@@ -1884,8 +1885,8 @@ multiclass VPseudoBinaryM_VX {
}
multiclass VPseudoBinaryM_VF {
- foreach m = MxList in
- foreach f = FPList in
+ foreach f = FPList in
+ foreach m = f.MxList in
defm "_V" # f.FX :
VPseudoBinaryM<VR, m.vrclass, f.fprclass, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
@@ -2209,8 +2210,8 @@ multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> {
}
multiclass VPseudoTernaryV_VF_AAXA<string Constraint = ""> {
- foreach m = MxList in
- foreach f = FPList in
+ foreach f = FPList in
+ foreach m = f.MxList in
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.vrclass, f.fprclass,
m.vrclass, m, Constraint,
/*Commutable*/1>;
@@ -2232,8 +2233,8 @@ multiclass VPseudoTernaryW_VX {
multiclass VPseudoTernaryW_VF {
defvar constraint = "@earlyclobber $rd";
- foreach m = MxListW in
- foreach f = FPListW in
+ foreach f = FPListW in
+ foreach m = f.MxList in
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass,
m.vrclass, m, constraint>;
}
@@ -4362,8 +4363,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let Predicates = [HasVInstructionsAnyF] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
- foreach m = MxList in {
- foreach f = FPList in {
+ foreach f = FPList in {
+ foreach m = f.MxList in {
let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
def "PseudoVFMV_" # f.FX # "_S_" # m.MX :
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