[PATCH] D116468: [AArch64] Combine ADD/SUB instructions when they contain a 24-bit immediate.

[Micah Weston via Phabricator via llvm-commits]

red1bluelost created this revision.
red1bluelost added reviewers: dmgreen, asavonic, SjoerdMeijer, paquette.
Herald added subscribers: hiraditya, kristof.beyls.
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Herald added a project: LLVM.

This patch combines improves add/sub instructions that have 24-bit
immediates by turning the MOV-MOV-ADD/SUB into ADDI/SUBI-ADDI/SUBI using the 
high and low 12-bit portions of the immediate.

For example, the following code:

  int addi(int A) { return A + 0x111333; }

results in the assembly:

  addi:                        // Without combine
          mov w8, #4915
          mov w8, #17, lsl #16
          add w0, w0, w8
          ret
  addi:                        // With combine
          add w8, w0, #273, lsl #12
          add w0, w8, #819
          ret

This was implemented by adding patterns to `MachineCombinerPattern` and
handling the patterns in `AArch64InstrInfo::genAlternativeCodeSequence` and
`AArch64InstrInfo::getMachineCombinerPatterns`. The patterns match for scenarios
where the moved-immediate is in operand 1 or 2 of the ADD/SUB, the immediate can
be negated to produce a 24-bit immediate which will change the ADD to SUB and
SUB to ADD, and where a SUBREG_TO_REG is used to promote the i32 register to
a i64 register.

I originally implemented this combine through a TableGen Pat however this
caused some of the MADD combines to fail. With the ADD/SUB combine residing
in the MachineCombiner, MADD combines can be prioritizes when both patterns
exist.

If this design is accepted, ADDS/SUBS patterns could be added in another patch.

Testing:

Each `MachineCombinerPattern` is tested `aarch64-combine-addsub-24bit-imm.mir`,
a new file.

The `addsub.ll` test file has the typical scenarios in LLVM IR.

I ran `ninja check-all` on the code.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116468

Files:
  llvm/include/llvm/CodeGen/MachineCombinerPattern.h
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/aarch64-combine-addsub-24bit-imm.mir
  llvm/test/CodeGen/AArch64/addsub.ll
  llvm/test/CodeGen/AArch64/and-mask-removal.ll
  llvm/test/CodeGen/AArch64/arm64-srl-and.ll
  llvm/test/CodeGen/AArch64/fast-isel-gep.ll
  llvm/test/CodeGen/AArch64/nontemporal.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll

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