[llvm] f8f5f1b - [Hexagon] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 31 15:17:35 PST 2021
Author: Kazu Hirata
Date: 2021-12-31T15:17:25-08:00
New Revision: f8f5f1b3a48e7497d8ff09ff35d3fd20a4c8c9b1
URL: https://github.com/llvm/llvm-project/commit/f8f5f1b3a48e7497d8ff09ff35d3fd20a4c8c9b1
DIFF: https://github.com/llvm/llvm-project/commit/f8f5f1b3a48e7497d8ff09ff35d3fd20a4c8c9b1.diff
LOG: [Hexagon] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 85230cac9d7c8..0bb1658e76983 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -583,14 +583,12 @@ namespace {
char HexagonGenInsert::ID = 0;
void HexagonGenInsert::dump_map() const {
- using iterator = IFMapType::const_iterator;
-
- for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- dbgs() << " " << printReg(I->first, HRI) << ":\n";
- const IFListType &LL = I->second;
- for (unsigned i = 0, n = LL.size(); i < n; ++i)
- dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", "
- << PrintRegSet(LL[i].second, HRI) << '\n';
+ for (const auto &I : IFMap) {
+ dbgs() << " " << printReg(I.first, HRI) << ":\n";
+ const IFListType &LL = I.second;
+ for (const auto &J : LL)
+ dbgs() << " " << PrintIFR(J.first, HRI) << ", "
+ << PrintRegSet(J.second, HRI) << '\n';
}
}
@@ -627,8 +625,8 @@ void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB,
using SortableVectorType = std::vector<unsigned>;
SortableVectorType VRs;
- for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I)
- VRs.push_back(I->first);
+ for (auto &I : RB)
+ VRs.push_back(I.first);
llvm::sort(VRs, LexCmp);
// Transfer the results to the outgoing register ordering.
for (unsigned i = 0, n = VRs.size(); i < n; ++i)
@@ -853,20 +851,18 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
if (isDebug()) {
dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";
- for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) {
- dbgs() << " L=" << I->first << ':';
- const RSListType &LL = I->second;
- for (unsigned i = 0, n = LL.size(); i < n; ++i)
- dbgs() << " (" << printReg(LL[i].first, HRI) << ",@"
- << LL[i].second << ')';
+ for (const auto &I : LM) {
+ dbgs() << " L=" << I.first << ':';
+ const RSListType &LL = I.second;
+ for (const auto &J : LL)
+ dbgs() << " (" << printReg(J.first, HRI) << ",@" << J.second << ')';
dbgs() << '\n';
}
}
bool Recorded = false;
- for (iterator I = AVs.begin(), E = AVs.end(); I != E; ++I) {
- unsigned SrcR = *I;
+ for (unsigned SrcR : AVs) {
int FDi = -1, LDi = -1; // First/last
diff erent bit.
const BitTracker::RegisterCell &AC = CMS->lookup(SrcR);
uint16_t AW = AC.width();
@@ -888,8 +884,8 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
if (F == LM.end())
continue;
RSListType &LL = F->second;
- for (unsigned i = 0, n = LL.size(); i < n; ++i) {
- uint16_t S = LL[i].second;
+ for (const auto &I : LL) {
+ uint16_t S = I.second;
// MinL is the minimum length of the prefix. Any length above MinL
// allows some flexibility as to where the prefix can start:
// given the extra length EL=L-MinL, the prefix must start between
@@ -900,7 +896,7 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
uint16_t LowS = (EL < FD) ? FD-EL : 0;
if (S < LowS) // Starts too early.
continue;
- unsigned InsR = LL[i].first;
+ unsigned InsR = I.first;
if (!isValidInsertForm(VR, SrcR, InsR, L, S))
continue;
if (isDebug()) {
@@ -1029,10 +1025,10 @@ void HexagonGenInsert::findRemovableRegisters(unsigned VR, IFRecord IF,
}
void HexagonGenInsert::computeRemovableRegisters() {
- for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- IFListType &LL = I->second;
- for (unsigned i = 0, n = LL.size(); i < n; ++i)
- findRemovableRegisters(I->first, LL[i].first, LL[i].second);
+ for (auto &I : IFMap) {
+ IFListType &LL = I.second;
+ for (auto &J : LL)
+ findRemovableRegisters(I.first, J.first, J.second);
}
}
@@ -1064,8 +1060,8 @@ void HexagonGenInsert::pruneCoveredSets(unsigned VR) {
MachineInstr *DefVR = MRI->getVRegDef(VR);
bool DefEx = HII->isConstExtended(*DefVR);
bool HasNE = false;
- for (unsigned i = 0, n = LL.size(); i < n; ++i) {
- if (LL[i].second.empty())
+ for (const auto &I : LL) {
+ if (I.second.empty())
continue;
HasNE = true;
break;
@@ -1172,8 +1168,8 @@ void HexagonGenInsert::pruneCandidates() {
// selection method.
// First, remove candidates whose potentially removable set is a subset
// of another candidate's set.
- for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I)
- pruneCoveredSets(I->first);
+ for (const auto &I : IFMap)
+ pruneCoveredSets(I.first);
UnsignedMap RPO;
@@ -1181,18 +1177,18 @@ void HexagonGenInsert::pruneCandidates() {
RPOTType RPOT(MFN);
unsigned RPON = 0;
- for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
- RPO[(*I)->getNumber()] = RPON++;
+ for (const auto &I : RPOT)
+ RPO[I->getNumber()] = RPON++;
PairMapType Memo; // Memoization map for distance calculation.
// Remove candidates that would use registers defined too far away.
- for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I)
- pruneUsesTooFar(I->first, RPO, Memo);
+ for (const auto &I : IFMap)
+ pruneUsesTooFar(I.first, RPO, Memo);
pruneEmptyLists();
- for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I)
- pruneRegCopies(I->first);
+ for (const auto &I : IFMap)
+ pruneRegCopies(I.first);
}
namespace {
@@ -1277,8 +1273,8 @@ void HexagonGenInsert::selectCandidates() {
for (IFMapType::iterator I = IFMap.begin(); I != End; ++I) {
const IFListType &LL = I->second;
RegisterSet TT;
- for (unsigned i = 0, n = LL.size(); i < n; ++i)
- TT.insert(LL[i].second);
+ for (const auto &J : LL)
+ TT.insert(J.second);
for (unsigned R = TT.find_first(); R; R = TT.find_next(R))
RemC[R]++;
AllRMs.insert(TT);
@@ -1384,8 +1380,8 @@ bool HexagonGenInsert::generateInserts() {
// Create a new register for each one from IFMap, and store them in the
// map.
UnsignedMap RegMap;
- for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- unsigned VR = I->first;
+ for (auto &I : IFMap) {
+ unsigned VR = I.first;
const TargetRegisterClass *RC = MRI->getRegClass(VR);
Register NewVR = MRI->createVirtualRegister(RC);
RegMap[VR] = NewVR;
@@ -1394,15 +1390,15 @@ bool HexagonGenInsert::generateInserts() {
// We can generate the "insert" instructions using potentially stale re-
// gisters: SrcR and InsR for a given VR may be among other registers that
// are also replaced. This is fine, we will do the mass "rauw" a bit later.
- for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- MachineInstr *MI = MRI->getVRegDef(I->first);
+ for (auto &I : IFMap) {
+ MachineInstr *MI = MRI->getVRegDef(I.first);
MachineBasicBlock &B = *MI->getParent();
DebugLoc DL = MI->getDebugLoc();
- unsigned NewR = RegMap[I->first];
+ unsigned NewR = RegMap[I.first];
bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;
const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)
: HII->get(Hexagon::S2_insertp);
- IFRecord IF = I->second[0].first;
+ IFRecord IF = I.second[0].first;
unsigned Wdh = IF.Wdh, Off = IF.Off;
unsigned InsS = 0;
if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {
@@ -1428,9 +1424,9 @@ bool HexagonGenInsert::generateInserts() {
MRI->clearKillFlags(IF.InsR);
}
- for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- MachineInstr *DefI = MRI->getVRegDef(I->first);
- MRI->replaceRegWith(I->first, RegMap[I->first]);
+ for (const auto &I : IFMap) {
+ MachineInstr *DefI = MRI->getVRegDef(I.first);
+ MRI->replaceRegWith(I.first, RegMap[I.first]);
DefI->eraseFromParent();
}
@@ -1523,9 +1519,8 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
if (isDebug()) {
dbgs() << "Cell ordering:\n";
- for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end();
- I != E; ++I) {
- unsigned VR = I->first, Pos = I->second;
+ for (const auto &I : CellOrd) {
+ unsigned VR = I.first, Pos = I.second;
dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 1a66394e97573..00615f355146e 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -505,8 +505,8 @@ bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
bool Changed = false;
collectPredicateGPR(MF);
- for (SetOfReg::iterator I = PredGPRs.begin(), E = PredGPRs.end(); I != E; ++I)
- processPredicateGPR(*I);
+ for (const RegisterSubReg &R : PredGPRs)
+ processPredicateGPR(R);
bool Again;
do {
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 5d2e1b259449e..338fda57c53ac 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1127,8 +1127,8 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
bool L1Used = false;
// Process nested loops first.
- for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
- Changed |= convertToHardwareLoop(*I, RecL0used, RecL1used);
+ for (MachineLoop *I : *L) {
+ Changed |= convertToHardwareLoop(I, RecL0used, RecL1used);
L0Used |= RecL0used;
L1Used |= RecL1used;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
index ed4874baf7c82..95e202647246e 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
@@ -230,8 +230,7 @@ bool Coloring::color() {
WorkQ.push_back(N);
}
- for (unsigned I = 0; I < WorkQ.size(); ++I) {
- Node N = WorkQ[I];
+ for (Node N : WorkQ) {
NodeSet &Ns = Edges[N];
auto P = getUniqueColor(Ns);
if (P.first) {
@@ -270,8 +269,7 @@ bool Coloring::color() {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void Coloring::dump() const {
dbgs() << "{ Order: {";
- for (unsigned I = 0; I != Order.size(); ++I) {
- Node P = Order[I];
+ for (Node P : Order) {
if (P != Ignore)
dbgs() << ' ' << P;
else
@@ -761,8 +759,7 @@ void ResultStack::print(raw_ostream &OS, const SelectionDAG &G) const {
namespace {
struct ShuffleMask {
ShuffleMask(ArrayRef<int> M) : Mask(M) {
- for (unsigned I = 0, E = Mask.size(); I != E; ++I) {
- int M = Mask[I];
+ for (int M : Mask) {
if (M == -1)
continue;
MinSrc = (MinSrc == -1) ? M : std::min(MinSrc, M);
@@ -935,8 +932,7 @@ static SmallVector<unsigned, 4> getInputSegmentList(ShuffleMask SM,
unsigned Shift = Log2_32(SegLen);
BitVector Segs(alignTo(SM.MaxSrc + 1, SegLen) >> Shift);
- for (int I = 0, E = SM.Mask.size(); I != E; ++I) {
- int M = SM.Mask[I];
+ for (int M : SM.Mask) {
if (M >= 0)
Segs.set(M >> Shift);
}
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