[PATCH] D116273: [AMDGPU] Iterate LoweredEndCf in the reverse order

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

What was the effect of inserting multiple branch instructions? Did it fail MIR verification?



================
Comment at: llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp:585
 
-  for (MachineInstr *MI : LoweredEndCf) {
+  for (MachineInstr *MI : llvm::reverse(LoweredEndCf)) {
     MachineBasicBlock &MBB = *MI->getParent();
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There's a "using namespace llvm" at the top of this file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116273/new/

https://reviews.llvm.org/D116273