[PATCH] D116421: [RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.

[Craig Topper via Phabricator via llvm-commits]

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This is similar to what is done for targets that prefer zero extend
where we avoid using a zero extend if the promoted values are sign
extended.

I've also applied these checks to ugt, ult, uge, and ule. This helps
the fpclamptosat tests for RV64, but did not affect any tests for other
targets.

While there I renamed the NewLHS and NewRHS variables to just LHS
and RHS. The 'New' only made sense in the context of them being
outputs of the function, but they are also inputs.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116421

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-convert.ll

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