[PATCH] D116397: [RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D116397#3213615 <https://reviews.llvm.org/D116397#3213615>, @asb wrote:

> This is a nice improvement. I'm seeing a few cases where additional moves are generated when this pass is enabled. Presumably this is exposing a problem elsewhere (or just a case where the register allocator is slightly less good) - but I'm wondering if you have looked at this at all?
>
> e.g. 20020529-1.c from the GCC torture suite:
>
>   --- a/output_rv64imafdc_lp64_O3/20020529-1.s
>   +++ b/output_rv64imafdc_lp64_O3/20020529-1.s
>   @@ -39,9 +39,10 @@ foo:                                    # @foo
>           bnez    a0, .LBB0_5
>    # %bb.9:                                # %if.end8.us.us
>                                            #   in Loop: Header=BB0_8 Depth=1
>   -       sext.w  a2, a4
>   -       addiw   a4, a4, 1
>   -       bne     a2, a1, .LBB0_8
>   +       addiw   a2, a4, 1
>   +       mv      a3, a4
>   +       mv      a4, a2
>   +       bne     a3, a1, .LBB0_8
>    .LBB0_10:                               # %if.then
>           lui     a0, %hi(f1.beenhere)
>           li      a1, 2

This looks like a bad scheduling decision. The NoSchedModel gave a latency of 1 for the sext.w, but a latency of 0 for the COPY that replaced it. With the latency of 1 the sext.w got scheduled before the addiw, with the latency of 0 the copy got scheduled after.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116397/new/

https://reviews.llvm.org/D116397