[PATCH] D116307: [RISCV] Teach VSETVLInsert to eliminate redundant vsetvli for vmv.s.x and vfmv.s.f.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 30 04:36:58 PST 2021
jacquesguan added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:470
+ case RISCV::PseudoVMV_S_X_MF8:
+ case RISCV::PseudoVFMV_F16_S_M1:
+ case RISCV::PseudoVFMV_F16_S_M2:
----------------
rogfer01 wrote:
> I'm confused by the commit title.
>
> You mention `vmv.s.x` which seems OK with the cases above and you also mention `vfmv.s.f`. But IIUC the cases listed here are for `vfmv.f.s`, right?
>
> This is my understanding after this exceprt from `RISCVInstrInfoVPseudos.td`
>
> ```
> //===----------------------------------------------------------------------===//
> // 17.2. Floating-Point Scalar Move Instructions
> //===----------------------------------------------------------------------===//
>
> let Predicates = [HasVInstructionsAnyF] in {
> foreach fvti = AllFloatVectors in {
> defvar instr = !cast<Instruction>("PseudoVFMV_"#fvti.ScalarSuffix#"_S_" #
> fvti.LMul.MX);
> def : Pat<(fvti.Scalar (int_riscv_vfmv_f_s (fvti.Vector fvti.RegClass:$rs2))),
> (instr $rs2, fvti.Log2SEW)>;
>
> def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1),
> (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),
> (!cast<Instruction>("PseudoVFMV_S_"#fvti.ScalarSuffix#"_" #
> fvti.LMul.MX)
> (fvti.Vector $rs1),
> (fvti.Scalar fvti.ScalarRegClass:$rs2),
> GPR:$vl, fvti.Log2SEW)>;
> }
> } // Predicates = [HasVInstructionsAnyF]
> ```
Yes, you are right. I used wrong cases here; I will create a new revision to fix this and add more test cases for floating point. Thank you very much.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D116307/new/
https://reviews.llvm.org/D116307
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