[PATCH] D116307: [RISCV] Teach VSETVLInsert to eliminate redundant vsetvli for vmv.s.x and vfmv.s.f.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:262
+         (hasZeroAVL() && InstrInfo.hasZeroAVL())) &&
+        hasSameSEW(InstrInfo) && hasSamePolicy(InstrInfo))
+      return true;
----------------
craig.topper wrote:
> The LMUL does matter if the policy is tail agnostic. If the last vsetvli has a larger lmul than the vmv.s.x instruction, then by ignoring LMUL you gave hardware permission to replace every element except 0 of the larger lmul with all 1s. But the vmv.s.x was only allowed to replace the smaller lmul.
> 
> I think there's also an issue if the register isn't aligned to a multiple of the LMUL setting in vtype. For example, if LMUL=8, the vmv.s.x can't use v2 as its register. Section 3.4.2 of the V spec says that is reserved.
> 
> ```
> When LMUL=8, the vector register group contains eight vector registers, and instructions specifying an LMUL=8 vector register group using register numbers that are not multiples of eight are reserved.
> ```
According to the spec: 
```
The instructions ignore LMUL and vector register groups. 
The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.
```
I think this means that these vector scalar move instructions only perform on a single vector register what ever the LMUL is.  And cause of ignoring the LMUL and vector group, it also can accept any vector register with any LMUL.


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  https://reviews.llvm.org/D116307/new/

https://reviews.llvm.org/D116307