[llvm] 43c8296 - [RISCV] Refactor immediate comparison instructions patterns
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 29 17:34:27 PST 2021
Author: Chenbing.Zheng
Date: 2021-12-30T09:31:01+08:00
New Revision: 43c8296cda97e0aee8668790ebe7b1b1d6c2b3f9
URL: https://github.com/llvm/llvm-project/commit/43c8296cda97e0aee8668790ebe7b1b1d6c2b3f9
DIFF: https://github.com/llvm/llvm-project/commit/43c8296cda97e0aee8668790ebe7b1b1d6c2b3f9.diff
LOG: [RISCV] Refactor immediate comparison instructions patterns
The patterns of the immediate comparison instruction is rewrite here, and put similar code to a class.
Do not change any function of the original code, making the code more concise.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D116215
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 073fa605e0fba..5b85d5adb1885 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3702,6 +3702,47 @@ multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
}
}
+multiclass VPatCompare_VI<string intrinsic, string inst> {
+ foreach vti = AllIntegerVectors in {
+ defvar Intr = !cast<Intrinsic>(intrinsic);
+ defvar Pseudo = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX);
+ def : Pat<(vti.Mask (Intr (vti.Vector vti.RegClass:$rs1),
+ (vti.Scalar simm5_plus1:$rs2),
+ VLOpFrag)),
+ (Pseudo vti.RegClass:$rs1, (DecImm simm5_plus1:$rs2),
+ GPR:$vl, vti.Log2SEW)>;
+ defvar IntrMask = !cast<Intrinsic>(intrinsic # "_mask");
+ defvar PseudoMask = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX#"_MASK");
+ def : Pat<(vti.Mask (IntrMask (vti.Mask VR:$merge),
+ (vti.Vector vti.RegClass:$rs1),
+ (vti.Scalar simm5_plus1:$rs2),
+ (vti.Mask V0),
+ VLOpFrag)),
+ (PseudoMask VR:$merge, vti.RegClass:$rs1, (DecImm simm5_plus1:$rs2),
+ (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
+ }
+}
+
+multiclass VPatCompareUnsignedZero<string intrinsic, string inst> {
+ foreach vti = AllIntegerVectors in {
+ defvar Intr = !cast<Intrinsic>(intrinsic);
+ defvar Pseudo = !cast<Instruction>(inst#"_VV_"#vti.LMul.MX);
+ def : Pat<(vti.Mask (Intr (vti.Vector vti.RegClass:$rs1),
+ (vti.Scalar 0), VLOpFrag)),
+ (Pseudo vti.RegClass:$rs1, vti.RegClass:$rs1,
+ GPR:$vl, vti.Log2SEW)>;
+ defvar IntrMask = !cast<Intrinsic>(intrinsic # "_mask");
+ defvar PseudoMask = !cast<Instruction>(inst#"_VV_"#vti.LMul.MX#"_MASK");
+ def : Pat<(vti.Mask (IntrMask (vti.Mask VR:$merge),
+ (vti.Vector vti.RegClass:$rs1),
+ (vti.Scalar 0),
+ (vti.Mask V0),
+ VLOpFrag)),
+ (PseudoMask VR:$merge, vti.RegClass:$rs1, vti.RegClass:$rs1,
+ (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
+ }
+}
+
//===----------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
@@ -4481,129 +4522,17 @@ defm : VPatBinarySwappedM_VV<"int_riscv_vmsge", "PseudoVMSLE", AllIntegerVectors
// Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16. This
// avoids the user needing to know that there is no vmslt(u).vi instruction.
// Similar for vmsge(u).vx intrinsics using vmslt(u).vi.
-foreach vti = AllIntegerVectors in {
- def : Pat<(vti.Mask (int_riscv_vmslt (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSLE_VI_"#vti.LMul.MX) vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- GPR:$vl,
- vti.Log2SEW)>;
- def : Pat<(vti.Mask (int_riscv_vmslt_mask (vti.Mask VR:$merge),
- (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- (vti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSLE_VI_"#vti.LMul.MX#"_MASK")
- VR:$merge,
- vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- (vti.Mask V0),
- GPR:$vl,
- vti.Log2SEW)>;
-
- def : Pat<(vti.Mask (int_riscv_vmsltu (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSLEU_VI_"#vti.LMul.MX) vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- GPR:$vl,
- vti.Log2SEW)>;
- def : Pat<(vti.Mask (int_riscv_vmsltu_mask (vti.Mask VR:$merge),
- (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- (vti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSLEU_VI_"#vti.LMul.MX#"_MASK")
- VR:$merge,
- vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- (vti.Mask V0),
- GPR:$vl,
- vti.Log2SEW)>;
-
- // Special cases to avoid matching vmsltu.vi 0 (always false) to
- // vmsleu.vi -1 (always true). Instead match to vmsne.vv.
- def : Pat<(vti.Mask (int_riscv_vmsltu (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar 0), VLOpFrag)),
- (!cast<Instruction>("PseudoVMSNE_VV_"#vti.LMul.MX) vti.RegClass:$rs1,
- vti.RegClass:$rs1,
- GPR:$vl,
- vti.Log2SEW)>;
- def : Pat<(vti.Mask (int_riscv_vmsltu_mask (vti.Mask VR:$merge),
- (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar 0),
- (vti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSNE_VV_"#vti.LMul.MX#"_MASK")
- VR:$merge,
- vti.RegClass:$rs1,
- vti.RegClass:$rs1,
- (vti.Mask V0),
- GPR:$vl,
- vti.Log2SEW)>;
-
- def : Pat<(vti.Mask (int_riscv_vmsge (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSGT_VI_"#vti.LMul.MX) vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- GPR:$vl,
- vti.Log2SEW)>;
- def : Pat<(vti.Mask (int_riscv_vmsge_mask (vti.Mask VR:$merge),
- (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- (vti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSGT_VI_"#vti.LMul.MX#"_MASK")
- VR:$merge,
- vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- (vti.Mask V0),
- GPR:$vl,
- vti.Log2SEW)>;
-
- def : Pat<(vti.Mask (int_riscv_vmsgeu (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSGTU_VI_"#vti.LMul.MX) vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- GPR:$vl,
- vti.Log2SEW)>;
- def : Pat<(vti.Mask (int_riscv_vmsgeu_mask (vti.Mask VR:$merge),
- (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar simm5_plus1:$rs2),
- (vti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSGTU_VI_"#vti.LMul.MX#"_MASK")
- VR:$merge,
- vti.RegClass:$rs1,
- (DecImm simm5_plus1:$rs2),
- (vti.Mask V0),
- GPR:$vl,
- vti.Log2SEW)>;
-
- // Special cases to avoid matching vmsgeu.vi 0 (always true) to
- // vmsgtu.vi -1 (always false). Instead match to vmsne.vv.
- def : Pat<(vti.Mask (int_riscv_vmsgeu (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar 0), VLOpFrag)),
- (!cast<Instruction>("PseudoVMSEQ_VV_"#vti.LMul.MX) vti.RegClass:$rs1,
- vti.RegClass:$rs1,
- GPR:$vl,
- vti.Log2SEW)>;
- def : Pat<(vti.Mask (int_riscv_vmsgeu_mask (vti.Mask VR:$merge),
- (vti.Vector vti.RegClass:$rs1),
- (vti.Scalar 0),
- (vti.Mask V0),
- VLOpFrag)),
- (!cast<Instruction>("PseudoVMSEQ_VV_"#vti.LMul.MX#"_MASK")
- VR:$merge,
- vti.RegClass:$rs1,
- vti.RegClass:$rs1,
- (vti.Mask V0),
- GPR:$vl,
- vti.Log2SEW)>;
-}
+defm : VPatCompare_VI<"int_riscv_vmslt", "PseudoVMSLE">;
+defm : VPatCompare_VI<"int_riscv_vmsltu", "PseudoVMSLEU">;
+// Special cases to avoid matching vmsltu.vi 0 (always false) to
+// vmsleu.vi -1 (always true). Instead match to vmsne.vv.
+defm : VPatCompareUnsignedZero<"int_riscv_vmsltu", "PseudoVMSNE">;
+
+defm : VPatCompare_VI<"int_riscv_vmsge", "PseudoVMSGT">;
+defm : VPatCompare_VI<"int_riscv_vmsgeu", "PseudoVMSGTU">;
+// Special cases to avoid matching vmsgeu.vi 0 (always true) to
+// vmsgtu.vi -1 (always false). Instead match to vmsne.vv.
+defm : VPatCompareUnsignedZero<"int_riscv_vmsgeu", "PseudoVMSEQ">;
//===----------------------------------------------------------------------===//
// 12.9. Vector Integer Min/Max Instructions
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