[PATCH] D116156: [AArch64] Adding "armv8.8-a" BC instruction.

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64.td:420
+def FeatureHBC : SubtargetFeature<"hbc", "HasHBC",
+    "true", "Enable Armv8.8-A hinted conditional branch instruction">;
+
----------------
nickdesaulniers wrote:
> Should this be `hinted branch conditional` to match HBC, or does the ARM ARM refer to it as such?
No, the name of the feature is "Hinted conditional branches" but it is referred to as FEAT_HBC.

https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools/feature-names-for-a-profile

However, I've updated the description to match the format used for the existing extensions.

I don't think there is a version of the Arm ARM with these extensions released yet, but I've added links to the A64 ISA docs to the description.


================
Comment at: llvm/test/MC/AArch64/armv8.8a-hbc.s:22
+        bc.le lbl
+        bc.al lbl
+
----------------
nickdesaulniers wrote:
> Do you need to define `lbl` somewhere?
Apparently not, but I've added it as a label for clarity.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116156/new/

https://reviews.llvm.org/D116156