[llvm] 015ff72 - [RISCV] Add a few more instructions to hasAllNBitUsers.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 29 09:31:51 PST 2021
Author: Craig Topper
Date: 2021-12-29T09:17:47-08:00
New Revision: 015ff729cb90317e4e75cf48b1e5dd7850f0cbd0
URL: https://github.com/llvm/llvm-project/commit/015ff729cb90317e4e75cf48b1e5dd7850f0cbd0
DIFF: https://github.com/llvm/llvm-project/commit/015ff729cb90317e4e75cf48b1e5dd7850f0cbd0.diff
LOG: [RISCV] Add a few more instructions to hasAllNBitUsers.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/atomic-signext.ll
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
llvm/test/CodeGen/RISCV/div-by-constant.ll
llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/usub_sat_plus.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index b24eb5f7bbf41..ab53c0eadfcfc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1727,6 +1727,20 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const {
if (Bits < Subtarget->getXLen() - User->getConstantOperandVal(1))
return false;
break;
+ case RISCV::ANDI:
+ if (Bits < (64 - countLeadingZeros(User->getConstantOperandVal(1))))
+ return false;
+ break;
+ case RISCV::SEXTB:
+ if (Bits < 8)
+ return false;
+ break;
+ case RISCV::SEXTH:
+ case RISCV::ZEXTH_RV32:
+ case RISCV::ZEXTH_RV64:
+ if (Bits < 16)
+ return false;
+ break;
case RISCV::ADDUW:
case RISCV::SH1ADDUW:
case RISCV::SH2ADDUW:
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index 131b3abf0fdfd..27262442d257a 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -2116,7 +2116,7 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -2264,7 +2264,7 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -2412,7 +2412,7 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -2560,7 +2560,7 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -2708,7 +2708,7 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -2856,7 +2856,7 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -3004,7 +3004,7 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i8_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -3152,7 +3152,7 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i8_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -3300,7 +3300,7 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -3448,7 +3448,7 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -6997,7 +6997,7 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -7147,7 +7147,7 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -7297,7 +7297,7 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -7447,7 +7447,7 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -7597,7 +7597,7 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -7747,7 +7747,7 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -7897,7 +7897,7 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i16_acquire:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -8047,7 +8047,7 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i16_release:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -8197,7 +8197,7 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -8347,7 +8347,7 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index 0347efeafbe5f..609863f127e88 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -696,7 +696,7 @@ define signext i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -850,7 +850,7 @@ define signext i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0
@@ -1753,7 +1753,7 @@ define signext i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
@@ -1909,7 +1909,7 @@ define signext i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
+; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1
diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
index a09b4d94558e1..4a08a7d3f1192 100644
--- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -173,7 +173,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV64I-NEXT: andi a0, a0, 51
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB3_2:
@@ -596,7 +596,7 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV64I-NEXT: andi a0, a0, 51
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: ret
%tmp = call i8 @llvm.cttz.i8(i8 %a, i1 true)
diff --git a/llvm/test/CodeGen/RISCV/div-by-constant.ll b/llvm/test/CodeGen/RISCV/div-by-constant.ll
index 5abae8fe3298b..8f354bd38b88b 100644
--- a/llvm/test/CodeGen/RISCV/div-by-constant.ll
+++ b/llvm/test/CodeGen/RISCV/div-by-constant.ll
@@ -200,7 +200,7 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
; RV64IM-NEXT: li a2, 37
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 8
-; RV64IM-NEXT: sub a0, a0, a1
+; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: andi a0, a0, 254
; RV64IM-NEXT: srli a0, a0, 1
; RV64IM-NEXT: add a0, a0, a1
@@ -213,7 +213,7 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
; RV64IMZB-NEXT: sh3add a2, a1, a1
; RV64IMZB-NEXT: sh2add a1, a2, a1
; RV64IMZB-NEXT: srli a1, a1, 8
-; RV64IMZB-NEXT: sub a0, a0, a1
+; RV64IMZB-NEXT: subw a0, a0, a1
; RV64IMZB-NEXT: andi a0, a0, 254
; RV64IMZB-NEXT: srli a0, a0, 1
; RV64IMZB-NEXT: add a0, a0, a1
@@ -310,7 +310,7 @@ define i16 @udiv16_constant_add(i16 %a) nounwind {
; RV64IMZB-NEXT: addiw a2, a2, 1171
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
-; RV64IMZB-NEXT: sub a0, a0, a1
+; RV64IMZB-NEXT: subw a0, a0, a1
; RV64IMZB-NEXT: zext.h a0, a0
; RV64IMZB-NEXT: srli a0, a0, 1
; RV64IMZB-NEXT: add a0, a0, a1
@@ -693,7 +693,7 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
; RV64IM-NEXT: li a2, -109
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 8
-; RV64IM-NEXT: add a0, a1, a0
+; RV64IM-NEXT: addw a0, a1, a0
; RV64IM-NEXT: andi a1, a0, 128
; RV64IM-NEXT: srli a1, a1, 7
; RV64IM-NEXT: slli a0, a0, 56
@@ -707,7 +707,7 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
; RV64IMZB-NEXT: li a2, -109
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 8
-; RV64IMZB-NEXT: add a0, a1, a0
+; RV64IMZB-NEXT: addw a0, a1, a0
; RV64IMZB-NEXT: andi a1, a0, 128
; RV64IMZB-NEXT: srli a1, a1, 7
; RV64IMZB-NEXT: sext.b a0, a0
@@ -757,7 +757,7 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
; RV64IM-NEXT: li a2, 109
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 8
-; RV64IM-NEXT: sub a0, a1, a0
+; RV64IM-NEXT: subw a0, a1, a0
; RV64IM-NEXT: andi a1, a0, 128
; RV64IM-NEXT: srli a1, a1, 7
; RV64IM-NEXT: slli a0, a0, 56
@@ -771,7 +771,7 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
; RV64IMZB-NEXT: li a2, 109
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 8
-; RV64IMZB-NEXT: sub a0, a1, a0
+; RV64IMZB-NEXT: subw a0, a1, a0
; RV64IMZB-NEXT: andi a1, a0, 128
; RV64IMZB-NEXT: srli a1, a1, 7
; RV64IMZB-NEXT: sext.b a0, a0
@@ -937,7 +937,7 @@ define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
; RV64IMZB-NEXT: addiw a2, a2, -1911
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
-; RV64IMZB-NEXT: add a0, a1, a0
+; RV64IMZB-NEXT: addw a0, a1, a0
; RV64IMZB-NEXT: zext.h a1, a0
; RV64IMZB-NEXT: srli a1, a1, 15
; RV64IMZB-NEXT: sext.h a0, a0
@@ -1003,7 +1003,7 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV64IMZB-NEXT: addiw a2, a2, 1911
; RV64IMZB-NEXT: mul a1, a1, a2
; RV64IMZB-NEXT: srli a1, a1, 16
-; RV64IMZB-NEXT: sub a0, a1, a0
+; RV64IMZB-NEXT: subw a0, a1, a0
; RV64IMZB-NEXT: zext.h a1, a0
; RV64IMZB-NEXT: srli a1, a1, 15
; RV64IMZB-NEXT: sext.h a0, a0
diff --git a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
index ac59d1087da21..bd7e50d6790c3 100644
--- a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
@@ -259,7 +259,7 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; RV64IZbb-LABEL: func16:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sext.h a0, a0
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: sext.h a1, a1
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: lui a1, 8
@@ -335,7 +335,7 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; RV64IZbb-LABEL: func8:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sext.b a0, a0
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: sext.b a1, a1
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: li a1, 127
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index 58b27218d6c8e..361fd88afbc67 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -244,9 +244,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
; RV64-NEXT: srai a1, a1, 58
; RV64-NEXT: srli a1, a1, 9
; RV64-NEXT: andi a1, a1, 3
-; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: addw a1, a0, a1
; RV64-NEXT: andi a1, a1, 60
-; RV64-NEXT: sub a0, a0, a1
+; RV64-NEXT: subw a0, a0, a1
; RV64-NEXT: andi a0, a0, 63
; RV64-NEXT: snez a0, a0
; RV64-NEXT: ret
@@ -270,9 +270,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
; RV64M-NEXT: srai a1, a1, 58
; RV64M-NEXT: srli a1, a1, 9
; RV64M-NEXT: andi a1, a1, 3
-; RV64M-NEXT: add a1, a0, a1
+; RV64M-NEXT: addw a1, a0, a1
; RV64M-NEXT: andi a1, a1, 60
-; RV64M-NEXT: sub a0, a0, a1
+; RV64M-NEXT: subw a0, a0, a1
; RV64M-NEXT: andi a0, a0, 63
; RV64M-NEXT: snez a0, a0
; RV64M-NEXT: ret
@@ -296,9 +296,9 @@ define i1 @test_srem_pow2_setne(i6 %X) nounwind {
; RV64MV-NEXT: srai a1, a1, 58
; RV64MV-NEXT: srli a1, a1, 9
; RV64MV-NEXT: andi a1, a1, 3
-; RV64MV-NEXT: add a1, a0, a1
+; RV64MV-NEXT: addw a1, a0, a1
; RV64MV-NEXT: andi a1, a1, 60
-; RV64MV-NEXT: sub a0, a0, a1
+; RV64MV-NEXT: subw a0, a0, a1
; RV64MV-NEXT: andi a0, a0, 63
; RV64MV-NEXT: snez a0, a0
; RV64MV-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll b/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
index 3ff18083e8d53..3393f2b01e53d 100644
--- a/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
@@ -258,7 +258,7 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; RV64IZbb-LABEL: func16:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sext.h a0, a0
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: sext.h a1, a1
; RV64IZbb-NEXT: sub a0, a0, a1
; RV64IZbb-NEXT: lui a1, 8
@@ -334,7 +334,7 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; RV64IZbb-LABEL: func8:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: sext.b a0, a0
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: sext.b a1, a1
; RV64IZbb-NEXT: sub a0, a0, a1
; RV64IZbb-NEXT: li a1, 127
diff --git a/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
index 3655564f16dc6..96d29b4b28829 100644
--- a/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
@@ -160,7 +160,7 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; RV64IZbb-LABEL: func16:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: zext.h a0, a0
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: zext.h a1, a1
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: lui a1, 16
@@ -189,7 +189,7 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; RV64I-LABEL: func8:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 255
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: andi a1, a1, 255
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: li a1, 255
@@ -212,7 +212,7 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; RV64IZbb-LABEL: func8:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: andi a0, a0, 255
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: andi a1, a1, 255
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: li a1, 255
@@ -240,7 +240,7 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; RV64I-LABEL: func4:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 15
-; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: mulw a1, a1, a2
; RV64I-NEXT: andi a1, a1, 15
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: li a1, 15
@@ -263,7 +263,7 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; RV64IZbb-LABEL: func4:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: andi a0, a0, 15
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: andi a1, a1, 15
; RV64IZbb-NEXT: add a0, a0, a1
; RV64IZbb-NEXT: li a1, 15
diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
index 6a9c674d9d2b5..8c3870ee4070f 100644
--- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
@@ -219,9 +219,9 @@ define i1 @test_urem_odd_setne(i4 %X) nounwind {
;
; RV64-LABEL: test_urem_odd_setne:
; RV64: # %bb.0:
-; RV64-NEXT: slli a1, a0, 1
-; RV64-NEXT: add a0, a1, a0
-; RV64-NEXT: neg a0, a0
+; RV64-NEXT: slliw a1, a0, 1
+; RV64-NEXT: addw a0, a1, a0
+; RV64-NEXT: negw a0, a0
; RV64-NEXT: andi a0, a0, 15
; RV64-NEXT: li a1, 3
; RV64-NEXT: sltu a0, a1, a0
@@ -239,9 +239,9 @@ define i1 @test_urem_odd_setne(i4 %X) nounwind {
;
; RV64M-LABEL: test_urem_odd_setne:
; RV64M: # %bb.0:
-; RV64M-NEXT: slli a1, a0, 1
-; RV64M-NEXT: add a0, a1, a0
-; RV64M-NEXT: neg a0, a0
+; RV64M-NEXT: slliw a1, a0, 1
+; RV64M-NEXT: addw a0, a1, a0
+; RV64M-NEXT: negw a0, a0
; RV64M-NEXT: andi a0, a0, 15
; RV64M-NEXT: li a1, 3
; RV64M-NEXT: sltu a0, a1, a0
@@ -259,9 +259,9 @@ define i1 @test_urem_odd_setne(i4 %X) nounwind {
;
; RV64MV-LABEL: test_urem_odd_setne:
; RV64MV: # %bb.0:
-; RV64MV-NEXT: slli a1, a0, 1
-; RV64MV-NEXT: add a0, a1, a0
-; RV64MV-NEXT: neg a0, a0
+; RV64MV-NEXT: slliw a1, a0, 1
+; RV64MV-NEXT: addw a0, a1, a0
+; RV64MV-NEXT: negw a0, a0
; RV64MV-NEXT: andi a0, a0, 15
; RV64MV-NEXT: li a1, 3
; RV64MV-NEXT: sltu a0, a1, a0
@@ -310,7 +310,7 @@ define i1 @test_urem_negative_odd(i9 %X) nounwind {
; RV64M-LABEL: test_urem_negative_odd:
; RV64M: # %bb.0:
; RV64M-NEXT: li a1, 307
-; RV64M-NEXT: mul a0, a0, a1
+; RV64M-NEXT: mulw a0, a0, a1
; RV64M-NEXT: andi a0, a0, 511
; RV64M-NEXT: li a1, 1
; RV64M-NEXT: sltu a0, a1, a0
@@ -328,7 +328,7 @@ define i1 @test_urem_negative_odd(i9 %X) nounwind {
; RV64MV-LABEL: test_urem_negative_odd:
; RV64MV: # %bb.0:
; RV64MV-NEXT: li a1, 307
-; RV64MV-NEXT: mul a0, a0, a1
+; RV64MV-NEXT: mulw a0, a0, a1
; RV64MV-NEXT: andi a0, a0, 511
; RV64MV-NEXT: li a1, 1
; RV64MV-NEXT: sltu a0, a1, a0
@@ -427,19 +427,19 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64-NEXT: li a1, 819
; RV64-NEXT: mv a0, s1
; RV64-NEXT: call __muldi3 at plt
-; RV64-NEXT: addi a0, a0, -1638
+; RV64-NEXT: addiw a0, a0, -1638
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 1
; RV64-NEXT: sltu s1, a1, a0
; RV64-NEXT: li a1, 1463
; RV64-NEXT: mv a0, s2
; RV64-NEXT: call __muldi3 at plt
-; RV64-NEXT: addi a0, a0, -1463
+; RV64-NEXT: addiw a0, a0, -1463
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 292
; RV64-NEXT: sltu a0, a1, a0
-; RV64-NEXT: neg a1, s3
-; RV64-NEXT: neg a0, a0
+; RV64-NEXT: negw a1, s3
+; RV64-NEXT: negw a0, a0
; RV64-NEXT: andi a1, a1, 2047
; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: slli a0, a0, 11
@@ -524,19 +524,19 @@ define void @test_urem_vec(<3 x i11>* %X) nounwind {
; RV64M-NEXT: li a4, 341
; RV64M-NEXT: sltu a1, a4, a1
; RV64M-NEXT: li a4, 819
-; RV64M-NEXT: mul a3, a3, a4
-; RV64M-NEXT: addi a3, a3, -1638
+; RV64M-NEXT: mulw a3, a3, a4
+; RV64M-NEXT: addiw a3, a3, -1638
; RV64M-NEXT: andi a3, a3, 2047
; RV64M-NEXT: li a4, 1
; RV64M-NEXT: sltu a3, a4, a3
; RV64M-NEXT: li a4, 1463
-; RV64M-NEXT: mul a2, a2, a4
-; RV64M-NEXT: addi a2, a2, -1463
+; RV64M-NEXT: mulw a2, a2, a4
+; RV64M-NEXT: addiw a2, a2, -1463
; RV64M-NEXT: andi a2, a2, 2047
; RV64M-NEXT: li a4, 292
; RV64M-NEXT: sltu a2, a4, a2
-; RV64M-NEXT: neg a1, a1
-; RV64M-NEXT: neg a2, a2
+; RV64M-NEXT: negw a1, a1
+; RV64M-NEXT: negw a2, a2
; RV64M-NEXT: andi a1, a1, 2047
; RV64M-NEXT: andi a2, a2, 2047
; RV64M-NEXT: slli a2, a2, 11
diff --git a/llvm/test/CodeGen/RISCV/usub_sat_plus.ll b/llvm/test/CodeGen/RISCV/usub_sat_plus.ll
index ef466dcc48373..42acda020cba1 100644
--- a/llvm/test/CodeGen/RISCV/usub_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/usub_sat_plus.ll
@@ -163,7 +163,7 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
; RV64IZbb-LABEL: func16:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: zext.h a0, a0
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: zext.h a1, a1
; RV64IZbb-NEXT: maxu a0, a0, a1
; RV64IZbb-NEXT: sub a0, a0, a1
@@ -190,7 +190,7 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; RV64I-LABEL: func8:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a3, a0, 255
-; RV64I-NEXT: mul a0, a1, a2
+; RV64I-NEXT: mulw a0, a1, a2
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: sub a1, a3, a0
; RV64I-NEXT: li a0, 0
@@ -212,7 +212,7 @@ define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
; RV64IZbb-LABEL: func8:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: andi a0, a0, 255
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: andi a1, a1, 255
; RV64IZbb-NEXT: maxu a0, a0, a1
; RV64IZbb-NEXT: sub a0, a0, a1
@@ -239,7 +239,7 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; RV64I-LABEL: func4:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a3, a0, 15
-; RV64I-NEXT: mul a0, a1, a2
+; RV64I-NEXT: mulw a0, a1, a2
; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: sub a1, a3, a0
; RV64I-NEXT: li a0, 0
@@ -261,7 +261,7 @@ define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
; RV64IZbb-LABEL: func4:
; RV64IZbb: # %bb.0:
; RV64IZbb-NEXT: andi a0, a0, 15
-; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: mulw a1, a1, a2
; RV64IZbb-NEXT: andi a1, a1, 15
; RV64IZbb-NEXT: maxu a0, a0, a1
; RV64IZbb-NEXT: sub a0, a0, a1
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