[PATCH] D116339: [RISCV] Add a command line option to control the LMUL used by TTI's getRegisterBitWidth.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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By default we return the width of an LMUL=1 register. We can enable
testing with larger LMUL values by returning a larger bit width.

This patch adds a RISCV specific option to provide a LMUL which will be
multiplied by the LMUL=1 bit width.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116339

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll

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