[PATCH] D116277: [RISCV] Use vmv.s.x to build one element splat vector.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll:187
 define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v32f16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    li a1, 32
-; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    lui a0, %hi(.LCPI10_0)
-; CHECK-NEXT:    addi a0, a0, %lo(.LCPI10_0)
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vlse16.v v12, (a0), zero
-; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
-; CHECK-NEXT:    vfredusum.vs v8, v8, v12
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
-; CHECK-NEXT:    ret
   %v = load <32 x half>, <32 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
----------------
The CHECK lines here disappeared


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll:212
 define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) {
-; CHECK-LABEL: vreduce_fadd_v64f16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    li a1, 64
-; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    lui a0, %hi(.LCPI12_0)
-; CHECK-NEXT:    addi a0, a0, %lo(.LCPI12_0)
-; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vlse16.v v16, (a0), zero
-; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT:    vfredusum.vs v8, v8, v16
-; CHECK-NEXT:    vfmv.f.s ft0, v8
-; CHECK-NEXT:    fadd.h fa0, fa0, ft0
-; CHECK-NEXT:    ret
   %v = load <64 x half>, <64 x half>* %x
   %red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
----------------
And here


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll:248
 ; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, mu
-; CHECK-NEXT:    vlse16.v v16, (a0), zero
+; CHECK-NEXT:    vfmv.s.f v16, ft0
 ; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu
----------------
This might be a regresson some microarchitectures.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116277/new/

https://reviews.llvm.org/D116277