[llvm] 0a5788a - [Target] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 26 23:49:49 PST 2021
Author: Kazu Hirata
Date: 2021-12-26T23:49:38-08:00
New Revision: 0a5788ab57464f1ec102c263aef2961175b084d0
URL: https://github.com/llvm/llvm-project/commit/0a5788ab57464f1ec102c263aef2961175b084d0
DIFF: https://github.com/llvm/llvm-project/commit/0a5788ab57464f1ec102c263aef2961175b084d0.diff
LOG: [Target] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
llvm/lib/Target/Hexagon/BitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 851acea94022b..fd79116e8009e 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -1123,9 +1123,8 @@ uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
DenseMap<unsigned, int> RegOffsets;
int FloatRegCount = 0;
// Process each .cfi directive and build up compact unwind info.
- for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
+ for (const MCCFIInstruction &Inst : Instrs) {
unsigned Reg;
- const MCCFIInstruction &Inst = Instrs[i];
switch (Inst.getOperation()) {
case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
CFARegisterOffset = Inst.getOffset();
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index e060e59e37596..0de5bf5d2d491 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -264,10 +264,8 @@ void ARMTargetAsmStreamer::emitInst(uint32_t Inst, char Suffix) {
void ARMTargetAsmStreamer::emitUnwindRaw(int64_t Offset,
const SmallVectorImpl<uint8_t> &Opcodes) {
OS << "\t.unwind_raw " << Offset;
- for (SmallVectorImpl<uint8_t>::const_iterator OCI = Opcodes.begin(),
- OCE = Opcodes.end();
- OCI != OCE; ++OCI)
- OS << ", 0x" << Twine::utohexstr(*OCI);
+ for (uint8_t Opcode : Opcodes)
+ OS << ", 0x" << Twine::utohexstr(Opcode);
OS << '\n';
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 05e5a473a3c62..17ca1866cf951 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -338,8 +338,8 @@ void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
{codeview::RegisterId::ARM_NQ14, ARM::Q14},
{codeview::RegisterId::ARM_NQ15, ARM::Q15},
};
- for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
- MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
+ for (const auto &I : RegMap)
+ MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
}
static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
index 1164b6ebbac3a..1cc5422523f17 100644
--- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -1147,9 +1147,8 @@ bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
// predecessors.
ReversePostOrderTraversal<MachineFunction*> RPOT(&MF);
bool Modified = false;
- for (ReversePostOrderTraversal<MachineFunction*>::rpo_iterator
- I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
- Modified |= ReduceMBB(**I);
+ for (MachineBasicBlock *MBB : RPOT)
+ Modified |= ReduceMBB(*MBB);
return Modified;
}
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 685bafd785dfb..17adf32750db6 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -940,8 +940,8 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
// If evaluated successfully add the targets to the cumulative list.
if (Trace) {
dbgs() << " adding targets:";
- for (unsigned i = 0, n = BTs.size(); i < n; ++i)
- dbgs() << " " << printMBBReference(*BTs[i]);
+ for (const MachineBasicBlock *BT : BTs)
+ dbgs() << " " << printMBBReference(*BT);
if (FallsThrough)
dbgs() << "\n falls through\n";
else
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 428d25da6dbc7..b2a842233bb86 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -3260,13 +3260,12 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
dbgs() << "Group[" << i << "] inp: "
<< printReg(G.Inp.Reg, HRI, G.Inp.Sub)
<< " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
- for (unsigned j = 0, m = G.Ins.size(); j < m; ++j)
- dbgs() << " " << *G.Ins[j];
+ for (const MachineInstr *MI : G.Ins)
+ dbgs() << " " << MI;
}
});
- for (unsigned i = 0, n = Groups.size(); i < n; ++i) {
- InstrGroup &G = Groups[i];
+ for (InstrGroup &G : Groups) {
if (!isShuffleOf(G.Out.Reg, G.Inp.Reg))
continue;
auto LoopInpEq = [G] (const PhiInfo &P) -> bool {
diff --git a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
index b456cf139c55c..a31ad45f4bb00 100644
--- a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
@@ -118,13 +118,10 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
return false;
// Loop over all of the basic blocks.
- for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
- MBBb != MBBe; ++MBBb) {
- MachineBasicBlock *MBB = &*MBBb;
-
+ for (MachineBasicBlock &MBB : Fn) {
// Traverse the basic block.
- MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
- if (MII != MBB->end()) {
+ MachineBasicBlock::iterator MII = MBB.getFirstTerminator();
+ if (MII != MBB.end()) {
MachineInstr &MI = *MII;
int Opc = MI.getOpcode();
if (IsConditionalBranch(Opc)) {
@@ -155,17 +152,17 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
// Remove BB2
// BB3: ...
// BB4: ...
- unsigned NumSuccs = MBB->succ_size();
- MachineBasicBlock::succ_iterator SI = MBB->succ_begin();
+ unsigned NumSuccs = MBB.succ_size();
+ MachineBasicBlock::succ_iterator SI = MBB.succ_begin();
MachineBasicBlock* FirstSucc = *SI;
MachineBasicBlock* SecondSucc = *(++SI);
MachineBasicBlock* LayoutSucc = nullptr;
MachineBasicBlock* JumpAroundTarget = nullptr;
- if (MBB->isLayoutSuccessor(FirstSucc)) {
+ if (MBB.isLayoutSuccessor(FirstSucc)) {
LayoutSucc = FirstSucc;
JumpAroundTarget = SecondSucc;
- } else if (MBB->isLayoutSuccessor(SecondSucc)) {
+ } else if (MBB.isLayoutSuccessor(SecondSucc)) {
LayoutSucc = SecondSucc;
JumpAroundTarget = FirstSucc;
} else {
@@ -201,7 +198,7 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
if (case1 || case2) {
InvertAndChangeJumpTarget(MI, UncondTarget);
- MBB->replaceSuccessor(JumpAroundTarget, UncondTarget);
+ MBB.replaceSuccessor(JumpAroundTarget, UncondTarget);
// Remove the unconditional branch in LayoutSucc.
LayoutSucc->erase(LayoutSucc->begin());
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index daf311fc49d47..105bf2811a20c 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -125,8 +125,8 @@ namespace {
};
LatticeCell() : Kind(Top), Size(0), IsSpecial(false) {
- for (unsigned i = 0; i < MaxCellSize; ++i)
- Values[i] = nullptr;
+ for (const Constant *&Value : Values)
+ Value = nullptr;
}
bool meet(const LatticeCell &L);
@@ -1029,8 +1029,8 @@ bool MachineConstPropagator::rewrite(MachineFunction &MF) {
ToRemove.push_back(const_cast<MachineBasicBlock*>(SB));
Targets.remove(SB);
}
- for (unsigned i = 0, n = ToRemove.size(); i < n; ++i)
- removeCFGEdge(B, ToRemove[i]);
+ for (MachineBasicBlock *MBB : ToRemove)
+ removeCFGEdge(B, MBB);
// If there are any blocks left in the computed targets, it means that
// we think that the block could go somewhere, but the CFG does not.
// This could legitimately happen in blocks that have non-returning
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 9a3feb5b6af18..2207925ceebaa 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -612,8 +612,8 @@ bool HexagonEarlyIfConversion::visitBlock(MachineBasicBlock *B,
// Simply keep a list of children of B, and traverse that list.
using DTNodeVectType = SmallVector<MachineDomTreeNode *, 4>;
DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
- for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
- MachineBasicBlock *SB = (*I)->getBlock();
+ for (auto &I : Cn) {
+ MachineBasicBlock *SB = I->getBlock();
if (!Deleted.count(SB))
Changed |= visitBlock(SB, L);
}
@@ -648,8 +648,8 @@ bool HexagonEarlyIfConversion::visitLoop(MachineLoop *L) {
<< "\n");
bool Changed = false;
if (L) {
- for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I)
- Changed |= visitLoop(*I);
+ for (MachineLoop *I : *L)
+ Changed |= visitLoop(I);
}
MachineBasicBlock *EntryB = GraphTraits<MachineFunction*>::getEntryNode(MFN);
@@ -964,8 +964,8 @@ void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) {
using DTNodeVectType = SmallVector<MachineDomTreeNode *, 4>;
DTNodeVectType Cn(GTN::child_begin(N), GTN::child_end(N));
- for (DTNodeVectType::iterator I = Cn.begin(), E = Cn.end(); I != E; ++I) {
- MachineBasicBlock *SB = (*I)->getBlock();
+ for (auto &I : Cn) {
+ MachineBasicBlock *SB = I->getBlock();
MDT->changeImmediateDominator(SB, IDB);
}
}
@@ -973,8 +973,8 @@ void HexagonEarlyIfConversion::removeBlock(MachineBasicBlock *B) {
while (!B->succ_empty())
B->removeSuccessor(B->succ_begin());
- for (auto I = B->pred_begin(), E = B->pred_end(); I != E; ++I)
- (*I)->removeSuccessor(B, true);
+ for (MachineBasicBlock *Pred : B->predecessors())
+ Pred->removeSuccessor(B, true);
Deleted.insert(B);
MDT->eraseNode(B);
@@ -1064,8 +1064,8 @@ bool HexagonEarlyIfConversion::runOnMachineFunction(MachineFunction &MF) {
Deleted.clear();
bool Changed = false;
- for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I)
- Changed |= visitLoop(*I);
+ for (MachineLoop *L : *MLI)
+ Changed |= visitLoop(L);
Changed |= visitLoop(nullptr);
return Changed;
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index c444cf557c217..2693940bb1e97 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -1106,8 +1106,7 @@ bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
}
bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
- for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
- LiveRange::Segment &LR = *I;
+ for (LiveRange::Segment &LR : LI) {
// Range must start at a register...
if (!LR.start.isRegister())
return false;
@@ -1160,16 +1159,16 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
// Move all live segments from L2 to L1.
using ValueInfoMap = DenseMap<VNInfo *, VNInfo *>;
ValueInfoMap VM;
- for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
- VNInfo *NewVN, *OldVN = I->valno;
+ for (LiveRange::Segment &I : L2) {
+ VNInfo *NewVN, *OldVN = I.valno;
ValueInfoMap::iterator F = VM.find(OldVN);
if (F == VM.end()) {
- NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator());
+ NewVN = L1.getNextValue(I.valno->def, LIS->getVNInfoAllocator());
VM.insert(std::make_pair(OldVN, NewVN));
} else {
NewVN = F->second;
}
- L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
+ L1.addSegment(LiveRange::Segment(I.start, I.end, NewVN));
}
while (!L2.empty())
L2.removeSegment(*L2.begin());
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 12ceac545e9df..a9520dcde88e2 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -416,8 +416,8 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
UnsignedMap RPO;
RPOTType RPOT(&MF);
unsigned RPON = 0;
- for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
- RPO[(*I)->getNumber()] = RPON++;
+ for (auto &I : RPOT)
+ RPO[I->getNumber()] = RPON++;
// Don't process functions that have loops, at least for now. Placement
// of prolog and epilog must take loop structure into account. For simpli-
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