[PATCH] D116039: [X86] Combine reduce (add (mul x, y)) to VNNI instruction.

LuoYuanke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 26 05:43:29 PST 2021


LuoYuanke added inline comments.


================
Comment at: llvm/test/CodeGen/X86/dpbusd.ll:13
+; AVXVNNI-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVXVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVXVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
----------------
LuoYuanke wrote:
> pengfei wrote:
> > This is the only and a strange diff with the AVX512 code. Is there anything wrong in one of each?
> This test doesn't generate vpdpbusd instruction, so the AVX512VNNI and AVX512VL generate the same code. For other test case, AVX512VNNI can only use zmm register, but AVX512VNNI + AVX512VL can use xmm register. 
For vpdpbusd_64xi32, the result is the same.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116039/new/

https://reviews.llvm.org/D116039



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