[PATCH] D115546: [RISCV][VP] Add RVV codegen for [nX]vXi1 vp.select

[Victor Perez via Phabricator via llvm-commits]

victor-eds updated this revision to Diff 395991.
victor-eds added a comment.

Unroll op if the operands are not i1 vectors


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115546/new/

https://reviews.llvm.org/D115546

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll

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