[llvm] 0489e89 - [DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
Shivam Gupta via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 22 21:19:59 PST 2021
Author: Shivam Gupta
Date: 2021-12-23T10:48:28+05:30
New Revision: 0489e891199afe766e6340be890b0d6cd91f0938
URL: https://github.com/llvm/llvm-project/commit/0489e891199afe766e6340be890b0d6cd91f0938
DIFF: https://github.com/llvm/llvm-project/commit/0489e891199afe766e6340be890b0d6cd91f0938.diff
LOG: [DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
When the source has a series of assignments, users reasonably want to
have the debugger step through each one individually. Turn off the combine
for adjacent stores so we get this behavior at -O0.
Similar to D7181.
Reviewed By: spatel, xgupta
Differential Revision: https://reviews.llvm.org/D115808
Added:
llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8055eb9a82d64..067ad819e0d26 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18395,8 +18395,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
if (ST->isUnindexed() && ST->isSimple() &&
ST1->isUnindexed() && ST1->isSimple()) {
- if (ST1->getBasePtr() == Ptr && ST1->getValue() == Value &&
- ST->getMemoryVT() == ST1->getMemoryVT() &&
+ if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr &&
+ ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() &&
ST->getAddressSpace() == ST1->getAddressSpace()) {
// If this is a store followed by a store with the same value to the
// same location, then the store is dead/noop.
diff --git a/llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll b/llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll
new file mode 100644
index 0000000000000..48e39a2593b7a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/optnone-store-no-combine.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+
+; This test verifies that a repeated store is not eliminated with optnone (improves debugging).
+
+define void @foo(i32* %p) noinline optnone {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 8
+; CHECK-NEXT: sw a1, 0(a0)
+; CHECK-NEXT: sw a1, 0(a0)
+; CHECK-NEXT: ret
+ store i32 8, i32* %p, align 4
+ store i32 8, i32* %p, align 4
+ ret void
+}
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